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When it comes to synthesis, initial values only apply to registers at power up(& memory cells). Initial values on wires is useless though ModelSim...

I have the same problem. I used Altera EP4CE6F17I7N, FBGA256 and EPCS4. I have all three supply voltage (VCCIO= 3.3V, VCCA= 2.5V, VCCD_PPL1,...

what licence do you have? a full version covers all versions of quartus.

you didnt pay for the full version of modelsim though. IIRC, AE only comes with a Quartus licecnce.

Thanks a lot, I've tried it and it made changes, but still can't exceed more than 10 M bit. Before it was 6 Mb as a max. now it's around 10 mb....

That would be a better way to get the data, but this actually a test architecture for transfer to a SATA HD. I haven't purchased a SATA IP yet, but...

If you are using a Windows host make sure to open the "Nios II Command Shell". You can find it in the start menu under the Nios II EDS you...

Hello, Thanks for the reply. Had re-done after deleting the same, but still getting the same results. 8.1 is the only license available with...

I'm wondering if it makes more sense to stream the data directly into SDRAM and avoid having the additional on-chip RAM and DMA in your design. if...

The queue scheduling would be responsible for that. So it's not that CvP is triggered by you calling any enqueuing function, it's when the need to...

What is the purpose of paying for a license if it limits you???!!!

Yes. The AE licence is limited, so when you have too large a design, it slows down simulation.

try deleting the /db and /incremental_db directories and try again. If that doesnt work, try a newer version (8.1 is several years old)

try deleting the /db and /incremental_db directories and try again. If that doesnt work, try a newer version (8.1 is several years old)

Thanks for your response BadOmen. I did use a ping pong approach (I think). I first stream 1600 bytes of data into onchip memory "DAQ1_MEM" with...

You can implement what you are after using the generate callback. Qsys/SOPC builder does not handle boolean and real valued generics in VHDL, and...

Thank you for the response. Actually, it had to do with trying to run it via Remote Desktop through a VPN. Apparently this isn't possible with...

The second issue has been resolved, I found non-corner PLLs, for example in Cyclone V E A7.

Perfect answer, Dave! Thanks for a great material!

yes it has m_tx_d2 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); if m_tx_d is not output, why it called tx

From what I'm seeing tether2 doesn't have a m_tx_d output. So instead of renaming it to m_tx_d2 you could keep the m_tx_d name. But anyway, this...

i wrap TSE in tether2 and connect m_tx_d => m_tx_d2 in order to connect less pins in top layer. output m_tx_d do not have any signal

Dear all With above commands i am able to create the list file But problem came when trying to generate multiple list files I am able to...