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Buckeye
April 13th, 2007, 12:05 PM
I want to re-program my epcs prom in the field. I see that I can do it using a nios design but I dont want to write nios software to do it. Is there a way to just write some hdl to connect to the internal prom lines the same way Nios does?

chuckbenz
April 13th, 2007, 12:27 PM
It's fairly easy using a nios design, and probably more complicated to do from HDL.

One way from HDL - instantiate an instance of the Serial Flash Loader (SFL) megafunction in your design. When you build the megafunction, enable the box for "Share the ASMI interface with your design".

Then you'll have to work out the logic to drive DCLK_IN, nCSO_IN, ASDO_IN, nOE_IN, and ASMI_ACCESS_GRANTED (inputs to the megafunction), and use DATA0_OUT and ASMI_ACCESS_REQUEST. I don't know if Altera provides much info on how to use these.

I found that putting epcs_controller in my NIOS system and using the epcs_commands.h commands was fairly simple. One hickup was that it was necessary to call epcs_write_enable before calling epcs_write_buffer, even though epcs_erase_sector didn't require that - it makes the write_enable call itself.

\chuck

Joe D
April 13th, 2007, 01:24 PM
If you don't want Nios, Serial Flashloader (SFL) is the solution you are asking for. This is a bridge function that allows the FPGA JTAG port to program the EPCS device that is attached to the FPGA. You can either have it present in your design all the time using the megafunction or QII can temporarily load a Serial Flash Loader image to the FPGA for you to bridge the programming of the EPCS through JTAG.

This app note should have the details of both although its a little tough to understand. You can convert a SOF (for your new design that you want in the EPCS) into a JIC file. That JIC file serves two function -> first part is the SFL bridging image which loads into the FPGA, the 2nd part of that file is the EPCS data that will pass through the bridge. Quartus should do this for you.

http://www.altera.com/literature/an/an370.pdf

Joe D
April 13th, 2007, 03:52 PM
Also, check this thread and attachment that I didn't notice was posted before this thread started...

http://www.alteraforum.com/forum/showthread.php?t=203

FPGA_GUY
April 17th, 2007, 01:32 PM
Here is an application note that addresses this topic.
http://www.altera.com/literature/an/an379.pdf

The secret is knowing that there is a hidden atom in the FPGA that allows you to access the EPCS pins through the FPGA fabric. In a Cyclone II device for example the atom is called cycloneii_asmiblock. This block will be recognized by Quartus and compile into your design.

A whole reference design exists in application note 379.

Joe D
April 17th, 2007, 03:18 PM
Thanks FG, this is much more clear than AN 370.

rcisnero
January 27th, 2008, 05:09 PM
To take AN370 one step further; can the Jam file generated to program the EPCS device be implemented by the JAM player within an external processor rather in place of Quartus?

Thanks

FvM
January 27th, 2008, 09:48 PM
Hello,

basically you can access SFL from an embedded processor, but you have to understand the virtual JTAG programming interface in FPGA. Alt_pfl and underlying sld_virtual_jtag Megafunction sources supplied with Qurtus give you some support, also the respective Megafunction user guides.

Some aspects of VJ are yet undocumented, but understandable to my opinion. I think however, that in-system programming through an embedded processor could better be achieved by accessing the AS interface directly, you just need a few tristate drivers, could be also tristatable PIO pins. As an advantage, this technique doesn't depend on previous succesful configuration of FPGA, thus could be used for initial programming in production and can recover in case of faulty configuration.

Regards,
Frank

davefrazer
February 10th, 2010, 01:42 PM
Are there any example designs that actually use the ASMI_ACCESS_REQUEST pin? It's always ignored in the application notes.

I have a few assumptions regading use of serial flash loader with user interface enabled:
1) if we don't really need to program the EPCS while the FPGA is configured and running, then we can simply never give it a grant. In that case the SFL simply gives our logic a means to access the EPCS
2) if JTAG is connected and attempts to program the EPCS then it is somehow connected, invisibly, to the block and causes the amsi_access_request signal to go true, and waits for a grant. Once granted, JTAG can program the EPCS