View Full Version : ADC interfacing and DDR_LVDS

January 9th, 2012, 04:19 PM
I'm currently developing on a ArriaII EVM together with an HSMC daughter card (TI's ADS62p29EVM through HSMC-ADC-bridge adapter). I need to use DDR LVDS for interfacing the cards.

But I'm a freshman with this interface and are confused about DDR LVDS.:confused: I want to see the actual waveform using signaltapII.

I added a DDRIO_in megafunction to interfacing the ADC chip.Pin IN[5:0] and INCLK are from ADS62P29 and SIGNAL_TAP_CLK is used in the signaltap clk.

But it can't compile successfully.I got a fitter error:Following 6 routing resources needed by more than one signal during the last fitting attempt.The 6 pins are IN[5:0].

Do I miss something like sdc or regenerator the INCLK in the PLL module, I really don't know how to find this information.

So many thanks.

January 9th, 2012, 06:47 PM
Seems to me these 6 pins are assigned to others signals as well in your design,apart from IN[5:0].

January 9th, 2012, 09:24 PM
Did you try to connect SignalTap to the DDR signals? That's not feasible, read the documentation. It's because DDIO inputs are directly connected to dedicated DDIO input registers, there's no routing option to tap the DDR input signal before splitting it into H and L signals.

January 9th, 2012, 10:54 PM
you mean I need use a SERDES module to split the DDR signal? Like LVDS_rx module first and set the deserialization factor by 2.

January 10th, 2012, 01:49 AM
You have alriady connected a 1:2 SERDES, or in other words DDIO registers. You can only tap the signal at the DDIO output, not the input.

January 10th, 2012, 02:36 AM
Thank you for your reply.

I'm so confused about the altlvds_rx and altDDIO module.
Implementing a DDR signal, 1:2 SERDES and DDIO module are both the same function?

however, DDIO do not have a internal PLL.Do I really need one ? or either is ok?

I have uploaded the ADC's waveform.Can I use the clkout_P or clkout_M directly with out pll?

thanks a lot.

January 10th, 2012, 03:23 AM
DDIO do not have a internal PLL
SERDES with factor 1:2 neither has if implemented in logic cells. With Arria/Stratix, you'll can use dedicated SERDES hardware and then need a PLL. This may be reasonable a highest speed, utilizing the SERDES dynamic phase alignment feature.

With SERDES in logic cells, which isn't but DDIO, differential CLKOUT can directly used as DDR sampling clock.

January 10th, 2012, 04:42 AM
Thank you very much.
I'll try the two methods.