Altera Forums

Regarding megafunction cycloneii_crcblock

ptangella42 — Fri, 18 May 2012 01:00:23 GMT

I am trying to access the CycloneII_crc block using the megafunction (cycloneii_crcblock). I have appended my code with this message. The code compiles and synthesize and maps properly. However, when I try to run the timing simulations the output of the crc-block CRC_ERROR, REGOUT, always remain at undefined state. I tried several combinations of shiftnld and ldsrc. I suplied 50MHZ clock in the waveform, I ran the simulation for up to 50ms (which takes about 5mins to run)

Any help will be appreciated.

Thank you in advance.

============my code=================================
module light(a, f, y, x1, x2,CLOCK_50, e, z,);
input a, x1, x2;
input CLOCK_50;
output f, y, z;
output e;
assign f=(x1&~x2)|(~x1&x2);
assign y= ~z;
cycloneii_crcblock XOR_research
(
.clk(CLOCK_50),
.shiftnld(a),
.ldsrc(f),
.crcerror(e),
.regout(z)
);

endmodule

Quartus II Web Edition installation problem on Fedora Core 17

tthtlc — Fri, 18 May 2012 00:41:05 GMT

Installation has a problem:

./11.1sp2_259_quartus_free_linux.sh
Creating directory 11.1sp2_259_quartus_free_linux
Verifying archive integrity... All good.
Uncompressing Quartus II Web Edition (Free)............................................ .................................................. .................................................. .................................................. .
Welcome to Altera Software Installer
Copyright (c) Altera Corporation 2011

Nothing started up, so looking at the trace file as indicated:

Traceback (most recent call last):
File "", line 14, in
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 436, in importHook
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 495, in doimport
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 297, in getmod
File "/tools/python/2.6.4/linux32/pyinstaller/archive.py", line 468, in getmod
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 109, in getmod
ImportError: libXext.so.6: cannot open shared object file: No such file or directory

My System:

FC 17 beta (64-bit) on AMD64-based motherboard. Is 64-bit a problem to install Quartus II web edition?

Problem with Always block

notooth — Fri, 18 May 2012 00:25:42 GMT

I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused:

Code:

 module main;

       bit a = 0;

       

       always @ (a==1)

           begin

                 // Run code

           end

 endmodule

Stratix IV PLL limits

vvr108 — Thu, 17 May 2012 21:57:25 GMT

Hi:

I have a 2 fpga stratix iv board and I want to generate a 1 MHz synchronous clock
in both. When I use the PLL, quartus refuses to let me give a clock slower than 5MHz
to the PLL. How can I do this with a PLL?

thanks.

EP600 programming

tfkeel — Thu, 17 May 2012 21:40:33 GMT

I used some of these about 20 years ago. The need has arisen to modify a program (one which I didn't write) and program a handful of chips with the new code.

Can someone tell me if I'm on the right tracks?

I think I can use MAX PLUS+2 for this. Also a program called PLDshell (which I think I used to use). It seems these two programs are easily available. Even though PLD is a dos program (?).

I think there should be folks around who still have programmers supporting this chip. My first approach will be to find someone I can send chips and a file to.

If that fails, second approach will be to buy a used programmer. Does anybody here know which ones support the chip?

Thanks.

Detecting Jtag connection

BillA — Thu, 17 May 2012 20:24:14 GMT

I want to be able to detect if the Jtag USB Blaster is connected, or if it is and connected to the NIOS II debugger. Is there a simple address to read to check for its presence?

I have my own I/O (printf, puts, gets, getchar, etc.) which I direct to Telnet if connected, RS-232 serial otherwise, unless there is a Jtag uart in which case I use it. I use my own Jtag serial code (because it's way more efficient and smaller). I notice Altera code runs a timer and clears the "presence" state if the timer times out and there is no Jtag activity (AC bit in Jtag control). I use my own code because I don't want the alt_alarm and ioctl baggage while still being able to detect if the Jtag is connected.

There has to be a better way than running a timer looking for activity. I set in my Jtag ISR a "JtagPresent" variable but when running in the debugger I don't get an interrupt to set this flag. This would be enough for me to know to use Jtag over the real serial port.

Is there a way using the hardware (not altera driver) to detect if the Jtag is present or not?

Thanks,
Bill

Read program from EP1810LC

Awann — Thu, 17 May 2012 19:07:58 GMT

Hello all, is it possible to read the programming file from an EP1810LC, save it and them use that file to program a different EP1810LC?

We have some old boards that we need to replicate, but the CPLD source code and programming files are whereabouts unknown (it was not our design).

Thanks in advance!

Graphical interface using NIOSII

patriciocordeiro — Thu, 17 May 2012 16:55:51 GMT

Hi,
i want to implement a software to control some buttons and leds via Graphical interface.
Can some one tell how to do this with NIOS.

thank you.

DE2 SDRAM/SOPC NiosII to Multisim help

latofte — Thu, 17 May 2012 16:09:27 GMT

Howdy, new to the forums, sorry if this is a repost but I could not find exactly what I was looking for.

My current goal
1. Create a VHDL design that can make use of the SDRAM on the DE2 development board.
2. Once it is shown to work on the LEDS I need to simulate it in mulitsim.

So far the best option I have found is to use the SOPC builder and add the SDRAM controller though the NiosII processor.
This and using the assembly file from the "Using the SDRAM memory on the Altera's DE2 Board with VHDL design" Altera Tutorial I was able to make the LEDS light up from the data sent to the SDRAM (part 1 complete)

However, I am having one hell of a time getting anything to run in multisim. Using the SOPC builder I tell it to also create simulation files when I create the SDRAM controller portion of the system, but there are read and write operations that make multisim fatal error before it can simulate.

So the last option I found was to follow these steps
In SOPC builder choose Tools --> Options...
once in here there is a dropdown menu that shows MentorGraphics ModelSim - Altera. which is what I want, but when try to choose the application path it will not let me actually choose the .exe file, it just will not show up.
So I tried just chosing the containg folder where the multisim.exe was located.

But obviously since i am posting here this refuses to work
I end up getting these 2 errors

Error: Could not find the simulator file unnamed_sim.mpf in \\mtucifs3\home\desktop\EET\AInternship\Sdram_Sopc Builder\JustSdram\unnamed_sim

Info: If you have not set the HDL Simulator Path (under Tools > Options), do so and regenerate.

Any help in this matter would be hugely appreciated :-P

Can CPU win arbitration during DMA operation to the same data bus?

YChan5 — Thu, 17 May 2012 15:39:36 GMT

Hi all

I am using the SOPC builder for my NIOS II system design.
I am having the 1Mx16 SSRAM and the 4Gb Nand Flash both sitting on the same data bus.
The SSRAM is for NIOS II cpu instruction and data. The Nand Flash is for storage of the acquistion data. Form time to time, I will be doing a DMA to burst 2K byte of data from the Nand Flash to an external IO port.

My question is: Can I do this without real time consequence.

While the DMA is in the middle of pulling 2K data from the flash, if the CPU also need to do read/write to the SSRAM, how will it impact the performance. Will the CPU need to wait all 2K of data pulled out before it can touch the SSRAM again. Or the CPU will win the arbitration and touch the SSRAM first before the DMA finish (such that the performance impact is minimize)?

Thanks
Steve Chan

Checksum for flash memory

GE_Bill — Thu, 17 May 2012 14:35:50 GMT

Greetings.

If I am pulling data from the EPCS64 How many bits can I pull off it at a time 8 , 16, 32?

Is there a quick and easy way to create a checksum to check the data? I've never implimented one before and am unsure where to start. Thanks

interleave two ad9288 to cyclone iii

lgeorge123 — Thu, 17 May 2012 14:02:28 GMT

I wish to connect two AD9288 (fast ADC) with interleave method , four clocks with 90 degree phase shift of 125MHz are connected to two AD9288 , their output are passed to cyclone iii FPGA for processing , so I ask if this equivalent to 500MHz signal input to cyclone iii ?? can they handled this fast I/O signal ???

PCIe and WinDriver problem

casamar — Thu, 17 May 2012 13:43:34 GMT

hi friends,

i have a problem if you can help me please:
i am working in the C IV GX fpga with the PCIe, i want to connect my board to the my host PC. for that , i'm using the windriver with MS visual studio.
i can read and write on the on-chip memory from the windriver's GUI, it works without any problem. but when i run the application generated by windriver in the MS Visual Studio it shows me this error :

DeviceOpen: Failed opening a handle to the device: Failed opening a WDC device handle. Error 0x2000000e - Resource overlap

i don't know how to resolve this problem.

pleace can you help me and thnx

Phase - NCO Calculation overtime

mue103 — Thu, 17 May 2012 12:38:54 GMT

I'm trying to determine the generic equation to determine what the phase (NCO output) should be after a certain number of clocks. The phase is derived from to accumulators. The FTW accumulator and NCO accumulator.

By using the distance equation "x = x0 + v0*t+(.5*a*t*t)-(.5*a*t)", I am able to calculate the phase if the FTW is always going in the positive or negative. What if the FTW is going both positive and negative (triangle or sawtooth wave)?

FYI...
x0 = 0
v0 = Starting Freq
a = Step Size
t = number of clocks

Quartusii compile

akira — Thu, 17 May 2012 11:29:41 GMT

Hi,

I am developing with cycloneIV.
The system contains large IPcores such as ATAN and DDRSDRAM.
It takes a while when I compile the project.

But matter is that when I compiled the project on the other PC.
The process failed because of memory space.

My pc has 8GB with Windows7 64bit OS
the other one os 4GB with WindowsXP 32 bit.

But 4GB is largest number for 32bit OS isn't it?

Do I need 64 bits OS as long as I maintain this kind of system?

i2c from altera wiki

YUFU0511 — Thu, 17 May 2012 08:51:53 GMT

Hi all

I've downloaded the i2c ip from altera wiki and simulated it in Nios II with ModelSim-Altera.

http://www.alterawiki.com/wiki/OpenCores_I2c

The attached picture is my simulation result.
My problem is why the sda and scl are always 0.

My C code is basically to enable the i2c ip and to send start condition, address(0x3f), and data.

Code:

I2C_init(OPENCORES_I2C_BASE, 100000000, 100000);

I2C_start(OPENCORES_I2C_BASE, 0x3f, 0); // 3f << 1

I2C_write(OPENCORES_I2C_BASE, 3, 0);

I2C_write(OPENCORES_I2C_BASE, 0xf0, 1);

From the simulation result, the prescale register becomes 0x00c7 as expected.
(100MHz/5/100KHz-1 = 0x00c7)
The register txr becomes 0x7e which stands for the slave address 0x3f and writing operation.
The status register shows TIP (transfer in progress) but there's no change on the sda and scl signals.

I check "i2c_master_bit_ctrl.v" and find the following code. I guess this is why sda and scal are always 0 but I'm not sure about it.

Code:

// assign scl and sda output (always gnd)

assign scl_o = 1'b0;

assign sda_o = 1'b0;

I believe there must be someone who has used this IP successfully.
Should I modify the verilog code and is there anything missing in my design?

Attached Images

i2c_nios2_sim.jpg (373.1 KB)

Problem with NIOS

i1020242 — Thu, 17 May 2012 08:49:30 GMT

I don't know operation
Ex:
Kiem_tra_N_va_Xuat_LED:
call CheckN1
call CheckN2
call CheckN3
call Check3N
call OutLED
br -44
Why br -44 ?????
Thank you everyone. Thank you very much

NIOS II IDE Problem

llwhrbust — Thu, 17 May 2012 05:03:52 GMT

hello,everyone!I'm new to NIOS II .I encountered a problem when I built a project recently.Here are the warnings:
Linking hello_world_0.elf...
1 [main] nios2-elf-g++ 9224 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0xC0000135, errno 11
1578603 [main] nios2-elf-g++ 9224 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0xC0000135, errno 11
3868304 [main] nios2-elf-g++ 9224 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0xC0000135, errno 11
8159532 [main] nios2-elf-g++ 9224 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0xC0000135, errno 11
nios2-elf-g++: fork: Resource temporarily unavailable
make: *** [hello_world_0.elf] Error 1
How can I solve this probem?thanks in advance!

PCIe HIP on Sandy Bridge E

jcosper — Thu, 17 May 2012 04:31:07 GMT

Hello all,

I am working on a project with SIV utilizing the PCIe 2.0 HIP as a legacy endpoint. Things have been working quite well for us at first, but recently we have run into an issue on certain platforms; specifically Sandy Bridge E.

With a LeCroy PCIe Analyzer, I see that a bad TLP is being sent to the Root Complex from our FPGA. Typically it has been a undefined format and type, but I have caught it as a CplLk TLP -- something my TLP-layer logic would not send. I used SignalTap to examine all the headers I send to the HIP and cannot find any issue in our code, and none of these bad headers. After this TLP is sent, all upstream TLPs are malformed -- they almost appears to be shifted (i.e. I see 0x4A00010 in the address field, a possible CplD).

I really don't know where to begin on this one. I have tried it on Sandy Bridge platforms and everything functions as expected (all under centOS). My next step is to use a reference design to see how it behaves in this system.

Has anyone else run into this problem? Any suggestions from the community? Thanks in advance.

Jay

Cyclone IV Programmer Failed

rgPaiva — Thu, 17 May 2012 00:52:48 GMT

Hi, i am trying to use Quartus 10.1 Programmer to transfer my code to the fpga (DE0-Nano) but i it says "Failed" all the time... i did the pin planner for the EP4CE6F17C6 using the ones from the DE0-Nano user manual,l but it uses EP4CE6F17C6N not EP4CE6F17C6, how can i solve this? Ty