Altera Forums - General Altera Discussion

Regarding megafunction cycloneii_crcblock

ptangella42 — Fri, 18 May 2012 01:00:23 GMT

I am trying to access the CycloneII_crc block using the megafunction (cycloneii_crcblock). I have appended my code with this message. The code compiles and synthesize and maps properly. However, when I try to run the timing simulations the output of the crc-block CRC_ERROR, REGOUT, always remain at undefined state. I tried several combinations of shiftnld and ldsrc. I suplied 50MHZ clock in the waveform, I ran the simulation for up to 50ms (which takes about 5mins to run)

Any help will be appreciated.

Thank you in advance.

============my code=================================
module light(a, f, y, x1, x2,CLOCK_50, e, z,);
input a, x1, x2;
input CLOCK_50;
output f, y, z;
output e;
assign f=(x1&~x2)|(~x1&x2);
assign y= ~z;
cycloneii_crcblock XOR_research
(
.clk(CLOCK_50),
.shiftnld(a),
.ldsrc(f),
.crcerror(e),
.regout(z)
);

endmodule

Problem with Always block

notooth — Fri, 18 May 2012 00:25:42 GMT

I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused:

Code:

 module main;

       bit a = 0;

       

       always @ (a==1)

           begin

                 // Run code

           end

 endmodule

Can CPU win arbitration during DMA operation to the same data bus?

YChan5 — Thu, 17 May 2012 15:39:36 GMT

Hi all

I am using the SOPC builder for my NIOS II system design.
I am having the 1Mx16 SSRAM and the 4Gb Nand Flash both sitting on the same data bus.
The SSRAM is for NIOS II cpu instruction and data. The Nand Flash is for storage of the acquistion data. Form time to time, I will be doing a DMA to burst 2K byte of data from the Nand Flash to an external IO port.

My question is: Can I do this without real time consequence.

While the DMA is in the middle of pulling 2K data from the flash, if the CPU also need to do read/write to the SSRAM, how will it impact the performance. Will the CPU need to wait all 2K of data pulled out before it can touch the SSRAM again. Or the CPU will win the arbitration and touch the SSRAM first before the DMA finish (such that the performance impact is minimize)?

Thanks
Steve Chan

Checksum for flash memory

GE_Bill — Thu, 17 May 2012 14:35:50 GMT

Greetings.

If I am pulling data from the EPCS64 How many bits can I pull off it at a time 8 , 16, 32?

Is there a quick and easy way to create a checksum to check the data? I've never implimented one before and am unsure where to start. Thanks

interleave two ad9288 to cyclone iii

lgeorge123 — Thu, 17 May 2012 14:02:28 GMT

I wish to connect two AD9288 (fast ADC) with interleave method , four clocks with 90 degree phase shift of 125MHz are connected to two AD9288 , their output are passed to cyclone iii FPGA for processing , so I ask if this equivalent to 500MHz signal input to cyclone iii ?? can they handled this fast I/O signal ???

Phase - NCO Calculation overtime

mue103 — Thu, 17 May 2012 12:38:54 GMT

I'm trying to determine the generic equation to determine what the phase (NCO output) should be after a certain number of clocks. The phase is derived from to accumulators. The FTW accumulator and NCO accumulator.

By using the distance equation "x = x0 + v0*t+(.5*a*t*t)-(.5*a*t)", I am able to calculate the phase if the FTW is always going in the positive or negative. What if the FTW is going both positive and negative (triangle or sawtooth wave)?

FYI...
x0 = 0
v0 = Starting Freq
a = Step Size
t = number of clocks

Cent OS 6.2 Support

fgnicodemos — Wed, 16 May 2012 22:31:04 GMT

Hi,

Does anybody knows when support for CenOS 6.2 will be available?
I am already using 6.2 but in website the supported OSs are only 4 and 5.

I have subscription full license.

Thanks,

Flashing NIOS Sw

MarkEverly — Wed, 16 May 2012 18:27:07 GMT

Have been debugging SW via JTAG port. Now that it works, would like to flash it. Am using eclipse and seem to recall that somewhere you can specify the load addresses. But can't seem to find where I configure it. Could someone point me in the right direction (What menu tree chain gets me there). Thanks in advance,
ME

HELP me in RS232

cycy — Wed, 16 May 2012 11:56:06 GMT

can anyone have a look in this coding.....my project using 2 de2-70 board. i want to send data captured from one de2-70 board to another de2-70 board by using rs232. anyone have done this before?urgent..can share some coding here?

registers in custom component and their address offset

YUFU0511 — Wed, 16 May 2012 05:47:35 GMT

Hi all

I'm wondering how NiosII defines the address offset for the registers in a custom component.

For example, I download a PWM verilog code from internet and generate a custom component which has an Avalon-MM interface to NiosII in Qsys component editor.

This is the PWM verilog code

Code:

module avalon_pwm(

        clk, 

        wr_data,

        cs,

        wr_n,

        addr,

        clr_n,

        rd_data,

        pwm_out

        );

        

        input clk;

        input [31:0]wr_data;

        input cs;

        input wr_n;

        input addr;

        input clr_n;

        output [31:0]rd_data;

        output pwm_out;

        

        reg [31:0]div;

        reg [31:0]duty;

        reg [31:0]counter;

        reg off;

        reg [31:0]rd_data;

        wire div_en;

        wire duty_en;

        

        // write div or duty 

        always@(posedge clk or negedge clr_n)

        begin

                if(clr_n == 1'b0)

                begin 

                        div <= 0;

                        duty <= 0;

                end

                else

                begin

                        if(div_en) div <= wr_data;

                        if(duty_en) duty <= wr_data;

                end

        end

        

        // counter

        always@(posedge clk or negedge clr_n)

        begin

                if(clr_n == 1'b0) counter <= 0;

                else if(counter >= (div-1)) counter <= 0;

                else counter <= counter + 1;

        end

        

        // PWM

        always@(posedge clk or negedge clr_n)

        begin

                if(clr_n == 0) off <= 0;

                else if(counter >= duty) off <= 1;

                else if(counter == 0) off <= 0;

        end

        

        // read div or duty

        always@(addr or div or duty)

        begin

                if(addr == 0) rd_data = div;

                else rd_data = duty;

        end

        

        assign div_en = cs & !wr_n & !addr;

        assign duty_en = cs & !wr_n & addr;

        assign pwm_out = !off;

        

endmodule

When I connect this PWM component to NiosII in Qsys and set the base address to 0x00041010, the end address becomes 0x00041017. So I guess there're 8 registers which can be accessed with the IOWR/IORD marcos by a C program on NiosII.

This is the code related to this PWM component in system.h

Code:

#define ALT_MODULE_CLASS_pwm avalon_pwm

#define PWM_BASE 0x41010

#define PWM_IRQ -1

#define PWM_IRQ_INTERRUPT_CONTROLLER_ID -1

#define PWM_NAME "/dev/pwm"

#define PWM_SPAN 8

#define PWM_TYPE "avalon_pwm"

I can use IOWR(PWM_BASE, 0, xxx) to set the div and IOWR(PWM_BASE, 1, xxx) to set the duty to have a PWM signal in different duty cycle.

My question is how to know which signals in the Verilog code are corresponding to the registers from 0x00041010 to 0x00041017.

Missing Chip Package

Workalot — Wed, 16 May 2012 04:47:23 GMT

Environment: Quartus II Web edition 9.1 SP2, MAX7000S series.

In the Device Selection dialog box the Available Devices list shows PLCC-44 and PLCC-84 packages but not the PLCC-68. Are there options for me?

Regards - Workalot

Chipselect in Avalon Interfaces

m13engr — Tue, 15 May 2012 20:51:26 GMT

Hi all,

I am getting used to using Quartus II and Qsys after being a long time Xilinx FPGA designer.

Question or request for clarification. Altera says in the Avalon Interface Spec that

"The chipselect signal is not necessary; Altera does not recommend using it."

I have a distributed architecture where several modules hang on the Avalon bus. I have assigned the memory map for each module and run a compilation without errors.

What I am not seeing is just how the memory map is applied to the distributed modules? I tried making the Avalon bus address the full 32 bits thinking that Qsys would use the upper addresses to partition the memory map assignments, but ran into problems. The memory map thought each module occupied the full 32 address bits and balked. So, I reduced the Address bus back to just the bits for that module.

I can see assigning Chipselects in the master and connecting each module to it's own chipselect, but this seems to fly in the face of Altera statement above about chipselects not being necessary.

Unfortunately, I am one of these guys that can't rest without a good understanding, and this one confuses me.

Any comment?

Thanks

Verilog task driving a bidirectional bus

jrdesign — Tue, 15 May 2012 19:46:53 GMT

I'm using SystemVerilog, writing a test bench to test a device that has a bidirectional bus. I have been successful directly writing a sequence of statements that put the data on the bus and pulse the write line. But that is cumbersome to write a lot of data. So I want to use the Verilog task capability. I can't seem to get it to drive the bus at all.
Here is the code simplified:

Code:

module test();

  wire [7:0] data;  // the bidirectional data bus

  reg wr;  // the write enable line

  logic [7:0] send_data; // the register for writing data



  my_device u1(

    .data,

    .wr

    );



  assign data = send_data;



  initial begin

    write_gpbus(8'h08);

  end



  task write_gpbus;

    input reg [7:0] data_to_send;

    begin

      send_data = data_to_send;

      #50ns wr = 1'b1;

      #50ns wr = 1'b0;

    end



endmodule

When I run this I can see send_data getting the correct value of the parameter passed into the task. But data (the actual bus) is always unknown, never gets a value.
If I were to just write directly to the send_data not using the task (as in the code below), then data does get the value. What am I doing wrong here?

Code:

  initial begin

    send_data = 8'h08;

  end

What Altera Dev board should I get?

templemark — Tue, 15 May 2012 13:16:35 GMT

I am looking to implement an embedded system which is going to control and orchestrate a whole bunch of fast switches on/off etc.

Main requirements are that I need to talk to the board via serial or Ethernet from a GUI. And I need some high speed ADC and DAC on board. (150Msps+) I also could use some transceivers to send signals to other boards. I also prob want to stick with cyclone family for their price/size.

I will probably code all the switching fabric in verilog and do the serial/ethernet communications with the Qsys/NIOS II.

I found this kit to be a possibility:
http://search.digikey.com/us/en/prod...566-ND/1832234

Only downside is that it is a cyclone III and doesnt have transceivers.

Any other suggestions?

Multi-Device AS Configuration with cyclone IV GX and cyclone III? +remote upgrade?

SebastienG — Tue, 15 May 2012 09:30:02 GMT

Hi,

I have a system using 2 different FPGA: 1 cyclone IV GX (master) and 1 cyclone III (slave). The cyclone IV uses AS configuration to boot from epcs and then programs the cyclone III in PS mode.
I would like to upgrade this system.

Is it possible to use a multi-Device AS Configuration with 2 different .sof with 2 different FPGA?
I also need to use the remote upgrade function. Is it compatible with multi-sof configuration?
I don't understand well how the FPGA manages multiple sof (epcs address, sof selection...), is there some examples?

I would like to use something like that:
-----EPCS-----
@0
.sof cycIV factory
.sof cycIII factory
@X
.sof cycIV user
.sof cycIII user
With remote upgrade function manage by cyclone IV.

Thanks in advance.

Yes No question (Using FPGA as a wire)

Drogio — Tue, 15 May 2012 08:59:34 GMT

1-Can I use FPGA, just as a wire, to carry a bidirectional line like I2C SDA from one pin of the FPGA to the other pin of the FPGA. In the FPGA there will not be an i2c master or slave it will just route the signal from one side to the other side. Both of the sides should be able to drive the SDA signal(bidirectional)

WHY :
I2c master and i2c slave is not physically connected to each other on the PCB BOARD. But they are physically connected to FPGA (Cyclone II EP2C20F484C8)

Attached Images

bidirectional.JPG (108.0 KB)

Problem with trigger

notooth — Tue, 15 May 2012 03:57:58 GMT

I compiled with an error in Quartus. Can anyone help me fix this issue?

Code:

 module main;

       event e;

       

       initial

          begin

             wait(e.triggered);  // Error here

          end

       

   endmodule

Code:

Error (10733): Verilog HDL error: triggered is not declared under this prefix

FPGA code for elevators(graduation project)

telecom_1234 — Mon, 14 May 2012 20:09:26 GMT

hey everybody,
im new to this forum as im new to altera and FPGA language.. i have been taking a course in univerisity ( 4th year telecom engineering) called "architecture of micropocesser and open core"

as a graduation project, i am thinking of doing a elevator board (lifts) in FPGA..
the question is:
-im i qualified to do it?
-is it realiable?
-and what do you think i should focus on ( as u know, a graduation project should have an added value.

thanks alot guys.. im already getting hooked to this forum.
looking forward for your answers

How to make business-related inquiries of Altera?

openasics — Mon, 14 May 2012 19:38:24 GMT

I'd like to contact Altera to inquire about using their HardCopy devices. I am aware of the technical documents available on the web site. My questions are of a business nature, not a technical nature.

I have searched the forum and web site for information on how to contact Altera about this topic, and have seen nothing other than a recommendation to contact my local field office. When I called my local field office, I was given only a list of names to choose from. I tried each of the names one at a time and was met only with voicemail each time, despite contacting them during normal business hours.

Can someone from Altera please contact me regarding this? Or at least provide me with suitable contact information so that I may try inquiring again? This would be for the Washington DC area.

Dual port RAM synchronisation

soundman32 — Mon, 14 May 2012 13:51:51 GMT

Sorry if this post is in the wrong group.

We have a system where a NIOS application communicates with a PC-104 style board via dual port RAM.

Some of our tests indicate that if the NIOS is writing to the ram at exactly the same time the PC-104 reads the same location, we sometimes get 'partial reads'.

For example, if the NIOS writes 0x81 to RAM, it is possible the PC will read 0x80, then a few cycles later, will read 0x81.

Our hardware guys (who designed the boards) say this is possible, but make out it's a software problem because we shouldn't be reading/writing to the same locations at the same time!

Firstly, can anyone give any more insight to the problem (is there really no synchronisation on dual port ram), and perhaps some pointers as to how to solve it?