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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 06:53 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 66,154
    April 7th, 2012, 02:36 PM Go to last post
    • Replies: 3
    • Views: 123
    Today, 08:46 AM Go to last post
  1. Read problem using LPDDR2 uniphy

    Started by DROR, August 28th, 2012 12:36 AM
    • Replies: 2
    • Views: 26,383
    Today, 08:44 AM Go to last post
  2. Arria V PCIe Hard IP sees stale data

    Started by bob_dixon, Today 07:28 AM
    • Replies: 0
    • Views: 38
    Today, 07:28 AM Go to last post
  3. rapidio Gen1 and rapidio Gen2

    Started by 41402169, Yesterday 07:40 PM
    • Replies: 0
    • Views: 91
    Yesterday, 07:40 PM Go to last post
  4. Using VIP suite with Triple Speed Ethernet (TSE)

    Started by Jalayan, October 8th, 2014 04:27 AM
    testpattern generator, triple speed ethernet, tse, vip suite, vlc
    • Replies: 9
    • Views: 900
    Yesterday, 04:56 AM Go to last post
  5. MPEG Transport stream over IP?

    Started by Nomex, September 4th, 2014 01:25 AM
    • Replies: 1
    • Views: 2,679
    October 20th, 2014, 03:01 AM Go to last post
  6. VIP Scaler and Clipper usage

    Started by dbdeset, August 6th, 2010 01:47 AM
    • Replies: 8
    • Views: 28,630
    October 19th, 2014, 09:30 PM Go to last post
  7. Refreshing older FPGA with Avalon OpenCores 10/100 Ethernet MAC

    Started by Ndnt, October 14th, 2014 07:17 AM
    • Replies: 3
    • Views: 572
    October 17th, 2014, 12:19 AM Go to last post
  8. Multiple (concatenated) DDR3 interface

    Started by stu1981, October 15th, 2014 06:17 AM
    • Replies: 0
    • Views: 489
    October 15th, 2014, 06:17 AM Go to last post
  9. Question Interfacing with Altera-MM Salve of UniPHY DDR2 controller

    Started by ter2, October 14th, 2014 12:02 AM
    avalon-mm, avl_ready, ddr2, slave, uniphy
    • Replies: 0
    • Views: 564
    October 14th, 2014, 12:02 AM Go to last post
  10. Simple question about SDI IP

    Started by faust861, May 23rd, 2014 01:25 AM
    • Replies: 7
    • Views: 5,952
    October 12th, 2014, 04:18 PM Go to last post
  11. CAS Latency on Cyclone V DDR2 Hard Memory Controller

    Started by Y0tsuya, October 10th, 2014 04:01 PM
    • Replies: 0
    • Views: 829
    October 10th, 2014, 04:01 PM Go to last post
    • Replies: 0
    • Views: 870
    October 9th, 2014, 12:18 AM Go to last post
  12. a question about the precharge operation of hpc ii?

    Started by happy053000, October 8th, 2014 06:39 PM
    • Replies: 0
    • Views: 895
    October 8th, 2014, 06:39 PM Go to last post
  13. Triple SDI RX - Clocked Video Input Interface

    Started by goksan.eral, September 28th, 2014 12:16 AM
    • Replies: 3
    • Views: 1,567
    October 8th, 2014, 05:33 PM Go to last post
  14. SD-SDI 8bit

    Started by Socrates, February 8th, 2011 12:44 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 25,373
    October 8th, 2014, 03:46 AM Go to last post
    • Replies: 0
    • Views: 933
    October 6th, 2014, 09:40 PM Go to last post
  15. QDRII+ UniPHY - Change afi_half_clk phase

    Started by TCWORLD, October 2nd, 2014 07:02 AM
    • Replies: 0
    • Views: 1,221
    October 2nd, 2014, 07:02 AM Go to last post
    • Replies: 1
    • Views: 1,589
    October 1st, 2014, 04:46 AM Go to last post
  16. NCO and Qsys

    Started by gaudetteje, September 19th, 2014 11:19 AM
    • Replies: 1
    • Views: 1,947
    September 29th, 2014, 11:56 PM Go to last post
  17. Stream to Memory sgdma problem

    Started by ecullert, May 1st, 2013 01:12 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 23,330
    September 29th, 2014, 08:59 AM Go to last post
  18. pciex4 ip core on cyclone iv gx F27

    Started by zlfeng1110, January 28th, 2012 02:03 AM
    • Replies: 9
    • Views: 27,900
    September 26th, 2014, 06:00 PM Go to last post
    • Replies: 3
    • Views: 5,410
    September 24th, 2014, 08:38 AM Go to last post
    • Replies: 0
    • Views: 2,068
    September 19th, 2014, 12:05 AM Go to last post
  19. PCIe interface with Nios II

    Started by mulligan252, September 15th, 2014 06:07 AM
    • Replies: 0
    • Views: 1,800
    September 15th, 2014, 06:07 AM Go to last post
  20. Chip Select CS_N in Uniphy ddr2 memory controller

    Started by YHubert, September 15th, 2014 05:10 AM
    • Replies: 0
    • Views: 1,844
    September 15th, 2014, 05:10 AM Go to last post
  21. problem with PCIe troughput in CIV GX DevKit

    Started by casamar, June 11th, 2012 05:51 AM
    • Replies: 5
    • Views: 28,595
    September 13th, 2014, 09:35 AM Go to last post
  22. Problems with "FIR Compiler" licensing

    Started by lethenstrom, September 8th, 2014 09:28 AM
    • Replies: 2
    • Views: 2,772
    September 11th, 2014, 09:46 AM Go to last post
  23. Intermediate Frequency

    Started by leeying.wu, September 7th, 2014 10:22 PM
    • Replies: 0
    • Views: 2,604
    September 7th, 2014, 10:22 PM Go to last post
  24. Question Interfacing SGDMA with custom component

    Started by haidarsoft, September 6th, 2014 03:14 AM
    custom component, q-sys, sgdma, write
    • Replies: 0
    • Views: 2,479
    September 6th, 2014, 03:14 AM Go to last post

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