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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 06:53 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 61,883
    April 7th, 2012, 02:36 PM Go to last post
  1. PCI Express help

    Started by mulligan252, July 25th, 2014 05:54 AM
    • Replies: 7
    • Views: 223
    Today, 08:47 AM Go to last post
  2. PCI Express board is not detected by lspci in linux

    Started by honda98, April 15th, 2012 11:01 PM
    • Replies: 5
    • Views: 18,477
    Yesterday, 05:37 PM Go to last post
  3. Simulating ALTFP_FP_ACC_CUSTOM core

    Started by chandru.m16, July 25th, 2014 08:38 PM
    • Replies: 0
    • Views: 251
    July 25th, 2014, 08:38 PM Go to last post
  4. DDR3 Performance changes with different pinout

    Started by pfrechette, May 23rd, 2014 02:45 PM
    ddr3, nios, stratix iv gx, uniphy
    • Replies: 5
    • Views: 1,801
    July 25th, 2014, 10:02 AM Go to last post
  5. Avalon MM Master simulation problem

    Started by rob18767, July 25th, 2014 09:49 AM
    • Replies: 0
    • Views: 286
    July 25th, 2014, 09:49 AM Go to last post
  6. ALTPLL for Cyclone III in Quartus 10.1 SP1

    Started by kboehme, July 25th, 2014 05:20 AM
    • Replies: 1
    • Views: 130
    July 25th, 2014, 05:55 AM Go to last post
  7. JESD204 interface

    Started by naka-t, November 12th, 2010 05:29 AM
    • Replies: 1
    • Views: 21,608
    July 22nd, 2014, 05:42 PM Go to last post
  8. Exclamation Bug in Chroma Resampler (Quartus version 13.0sp1)

    Started by jamo, July 22nd, 2014 09:07 AM
    chroma resampler vip
    • Replies: 0
    • Views: 302
    July 22nd, 2014, 09:07 AM Go to last post
  9. Question DDR2 with Cyclone V

    Started by B0RT, April 17th, 2014 07:31 AM
    cyclone v, ddr2, megawizzard
    • Replies: 1
    • Views: 2,275
    July 21st, 2014, 05:46 PM Go to last post
  10. Qsys PCIe core fails timing

    Started by dwh@ovro.caltech.edu, May 4th, 2012 02:42 PM
    3 Pages
    1 2 3
    • Replies: 21
    • Views: 33,311
    July 21st, 2014, 10:13 AM Go to last post
    • Replies: 1
    • Views: 809
    July 21st, 2014, 07:57 AM Go to last post
  11. Arria V Transceiver Reconfiguration Registers

    Started by graych, July 15th, 2014 07:41 AM
    map, reconfiguration, register, transceiver, xcvr
    • Replies: 4
    • Views: 766
    July 21st, 2014, 07:27 AM Go to last post
    • Replies: 1
    • Views: 1,233
    July 20th, 2014, 05:54 AM Go to last post
  12. Problem with credits for PCIE IP

    Started by glennramalho, July 15th, 2014 11:55 AM
    • Replies: 1
    • Views: 657
    July 20th, 2014, 05:27 AM Go to last post
    • Replies: 0
    • Views: 466
    July 19th, 2014, 06:56 AM Go to last post
  13. SGDMA Memory to Stream Problem

    Started by Ayesha89, July 17th, 2014 12:50 AM
    • Replies: 0
    • Views: 367
    July 17th, 2014, 12:50 AM Go to last post
    • Replies: 1
    • Views: 610
    July 15th, 2014, 09:40 AM Go to last post
  14. 2D FIR filter test bench address out of bound

    Started by lucask07, July 10th, 2014 11:15 AM
    • Replies: 3
    • Views: 438
    July 10th, 2014, 12:57 PM Go to last post
    • Replies: 0
    • Views: 531
    July 10th, 2014, 02:19 AM Go to last post
  15. TSE RX Problem

    Started by sebwelzel, July 8th, 2014 04:12 AM
    • Replies: 1
    • Views: 748
    July 10th, 2014, 01:20 AM Go to last post
  16. Altera DMA throughput calculation?

    Started by aprado, July 9th, 2014 05:09 AM
    • Replies: 1
    • Views: 680
    July 9th, 2014, 05:39 AM Go to last post
  17. Custom PHY simulation

    Started by Lancer, July 9th, 2014 12:15 AM
    • Replies: 0
    • Views: 694
    July 9th, 2014, 12:15 AM Go to last post
    • Replies: 1
    • Views: 16,767
    July 7th, 2014, 05:47 PM Go to last post
    • Replies: 6
    • Views: 3,384
    July 7th, 2014, 04:28 PM Go to last post
    • Replies: 1
    • Views: 980
    July 7th, 2014, 04:32 AM Go to last post
  18. Avalon-ST Splitter in VIP cause issues

    Started by lanix, May 16th, 2014 01:38 AM
    • Replies: 1
    • Views: 2,402
    July 7th, 2014, 12:46 AM Go to last post
    • Replies: 1
    • Views: 530
    July 6th, 2014, 10:52 PM Go to last post
  19. Unresolved module

    Started by FPGA Newbie, July 4th, 2014 01:49 AM
    • Replies: 0
    • Views: 802
    July 4th, 2014, 01:49 AM Go to last post
    • Replies: 6
    • Views: 1,686
    July 3rd, 2014, 10:34 PM Go to last post
  20. JESD Transport layer reconfigurability

    Started by CG6991, July 3rd, 2014 03:10 AM
    • Replies: 0
    • Views: 1,417
    July 3rd, 2014, 03:10 AM Go to last post

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