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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 06:53 PM
    2 Pages •
    1 2
    • Replies: 14
    • Views: 38,047
    plmt2011
    April 7th, 2012, 02:36 PM Go to last post

  1. Issues with Interlaken PHY on Stratix V

    Started by romno, Today 07:51 PM
    interlaken, stratix v, transceiver
    • Replies: 0
    • Views: 1
    romno
    Today, 07:51 PM Go to last post

  2. PCIe IP with 2 VCs, Vendor ID only on VC0?

    Started by Shvitzer, Today 08:04 AM
    • Replies: 0
    • Views: 50
    Shvitzer
    Today, 08:04 AM Go to last post

  3. SDI II Core, Reconfiguration does not work. Reconfig_busy stays low

    Started by fixation, February 19th, 2013 01:16 AM
    • Replies: 3
    • Views: 4,324
    DRC
    Yesterday, 05:22 AM Go to last post

  4. use descriptor chain in SGDMA

    Started by YUFU0511, June 15th, 2012 12:15 AM
    2 Pages •
    1 2
    • Replies: 16
    • Views: 10,331
    dmehta
    June 17th, 2013, 12:37 PM Go to last post

  5. how to use the GXB interfaces in stratixV?

    Started by shiika, May 17th, 2013 01:05 AM
    • Replies: 1
    • Views: 1,686
    fpga89
    June 15th, 2013, 05:11 PM Go to last post

  6. Question Custom Phy with stratix V GS

    Started by Angad Shah, May 22nd, 2013 11:37 PM
    10g, custom phy, stratix v
    • Replies: 1
    • Views: 1,336
    fpga89
    June 15th, 2013, 05:10 PM Go to last post

  7. TCP/IP Offload Engine Implementations -- What's the big deal?

    Started by mosfet2474, June 12th, 2013 06:00 AM
    • Replies: 4
    • Views: 447
    Daixiwen
    June 14th, 2013, 04:58 AM Go to last post

  8. TSE RGMII rxdv error

    Started by vasek_pilsen, April 16th, 2013 12:34 AM
    1 Attachment(s)
    • Replies: 8
    • Views: 3,516
    almemar
    June 14th, 2013, 01:40 AM Go to last post

  9. TSE (Ethernet) - Core does not transmit data on RGMII TX, rest works perfectly fine

    Started by sf_2010, April 29th, 2013 07:38 AM
    1 Attachment(s)
    • Replies: 9
    • Views: 2,751
    DaveHorne
    June 13th, 2013, 12:46 AM Go to last post

  10. DDR3 IP simulation error Error: (vsim-10000) Unresolved defparamreference to 'power_s

    Started by kushal.chaudhari, June 13th, 2013 12:11 AM
    • Replies: 0
    • Views: 300
    kushal.chaudhari
    June 13th, 2013, 12:11 AM Go to last post

  11. altera 13.0 uniphy pin assign script fails if adv_netlist_opt_synth_gate_retime is on

    Started by JeffreyOHill, June 12th, 2013 10:04 AM
    13.0, assignment, pin, uniphy
    • Replies: 0
    • Views: 353
    JeffreyOHill
    June 12th, 2013, 10:04 AM Go to last post

  12. Problem with FFT of 32768 points and more

    Started by LETS, June 12th, 2013 06:18 AM
    3 Attachment(s)
    • Replies: 0
    • Views: 388
    LETS
    June 12th, 2013, 06:18 AM Go to last post

  13. PCIe hard IP - MSI-X Capabilities are incorrect

    Started by RalfGoebel, June 12th, 2013 04:17 AM
    pcie
    • Replies: 0
    • Views: 365
    RalfGoebel
    June 12th, 2013, 04:17 AM Go to last post

  14. What should be the maximum port data width of DDR3 Uniphyfor DDR3 MT41J128M16 SDRAM?

    Started by kushal.chaudhari, June 11th, 2013 06:21 AM
    • Replies: 0
    • Views: 435
    kushal.chaudhari
    June 11th, 2013, 06:21 AM Go to last post

  15. PCI express electrical testing

    Started by rob18767, June 10th, 2013 07:32 AM
    • Replies: 0
    • Views: 424
    rob18767
    June 10th, 2013, 07:32 AM Go to last post

  16. WLAN AHB bridge , AMBA

    Started by devilesence, June 8th, 2013 05:31 AM
    ahb bridge, amba, arm, wlan ahb bridge
    • Replies: 1
    • Views: 568
    devilesence
    June 8th, 2013, 07:54 AM Go to last post

  17. Clocked Video IP for NTSC bt656

    Started by Nadeem, October 21st, 2008 08:16 AM
    2 Pages •
    1 2
    3 Attachment(s)
    • Replies: 13
    • Views: 37,421
    lrp
    June 7th, 2013, 06:58 AM Go to last post

  18. Lightbulb how to ENABLE/DISABLE parts of an IP-core depending on the instance parameters??

    Started by MrFreshman, May 23rd, 2013 05:36 AM
    generic, instance parameter, instance script, ip-core, qsys 2 Attachment(s)
    • Replies: 6
    • Views: 1,471
    dwh@ovro.caltech.edu
    June 6th, 2013, 08:28 AM Go to last post

  19. PCIe Hardip going from x1-to-x4 Error "transmit_pcs0" has illegal fan-out

    Started by Shvitzer, June 5th, 2013 07:23 AM
    • Replies: 1
    • Views: 634
    Shvitzer
    June 6th, 2013, 07:47 AM Go to last post

  20. difference between quartus II systhesis tool and synopsis design compiler

    Started by JenC, May 28th, 2013 08:09 PM
    • Replies: 2
    • Views: 1,151
    JenC
    June 6th, 2013, 12:23 AM Go to last post

  21. PCIe Endpoint requester

    Started by alexis91, June 5th, 2013 04:31 AM
    enpoint, pci express, pcie 1 Attachment(s)
    • Replies: 1
    • Views: 706
    alexis91
    June 5th, 2013, 04:32 AM Go to last post

  22. Unhappy pcie hardip Lane Reversal

    Started by diego01, September 7th, 2011 01:44 AM
    2 Pages •
    1 2
    1 Attachment(s)
    • Replies: 11
    • Views: 9,273
    Aphraton
    June 5th, 2013, 03:57 AM Go to last post

  23. Phase alignment reference using ALTPLL and ALTPLL_RECONFIG modules

    Started by romlef, June 4th, 2013 01:40 AM
    • Replies: 1
    • Views: 689
    romlef
    June 5th, 2013, 12:07 AM Go to last post

  24. DDR2 SDRAM Controller with ALTMEMPHY signals

    Started by awelters, June 4th, 2013 10:00 AM
    • Replies: 0
    • Views: 650
    awelters
    June 4th, 2013, 10:00 AM Go to last post

  25. HARD IP PCIex STRATIX IV , DMA with data jumgled

    Started by didier_m06, June 4th, 2013 06:26 AM
    "pciex" "jumbled" "dma"
    • Replies: 0
    • Views: 740
    didier_m06
    June 4th, 2013, 06:26 AM Go to last post

  26. Question PCIe hard IP endpoint with hpg_ctrler signal

    Started by SimonRichter, June 4th, 2013 12:10 AM
    pcie hardip 1 Attachment(s)
    • Replies: 0
    • Views: 673
    SimonRichter
    June 4th, 2013, 12:10 AM Go to last post

  27. PCIe x8 Gen2 for Stratix IV (usng QSys)

    Started by eldos, June 3rd, 2013 10:24 AM
    • Replies: 2
    • Views: 907
    eldos
    June 3rd, 2013, 12:28 PM Go to last post

  28. multiple xaui interfaces

    Started by cronus10, December 27th, 2012 01:35 PM
    • Replies: 3
    • Views: 5,674
    comododragon
    June 1st, 2013, 05:23 PM Go to last post

  29. Question Difference between DDR2 SDRAM controller with ALTMEMPHY and with UNIPHY

    Started by trupesh.vasoya, May 31st, 2013 04:08 AM
    • Replies: 0
    • Views: 893
    trupesh.vasoya
    May 31st, 2013, 04:08 AM Go to last post

  30. True Dual Port RAM

    Started by Gio_Faz, May 30th, 2013 02:53 AM
    • Replies: 6
    • Views: 1,041
    Gio_Faz
    May 31st, 2013, 02:50 AM Go to last post
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