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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 06:53 PM
    2 Pages
    1 2
    using tse ip core
    • Replies: 16
    • Views: 84,080
    June 9th, 2015, 07:50 AM Go to last post
  1. Library auk_dspip_lib not found

    Started by Vector Huang, Yesterday 04:36 AM
    • Replies: 0
    • Views: 31
    Yesterday, 04:36 AM Go to last post
  2. PCIe IO BAR's limited to "Legacy Endpoints"

    Started by bob_dixon, April 29th, 2016 11:39 AM
    bar, iospace, pcie, stratix
    • Replies: 3
    • Views: 85
    May 1st, 2016, 03:54 PM Go to last post
    • Replies: 6
    • Views: 132
    April 28th, 2016, 07:08 AM Go to last post
  3. fft megacore core giving all HI-Z to all output signals

    Started by vhdlhog, April 25th, 2016 07:45 PM
    • Replies: 0
    • Views: 42
    April 25th, 2016, 07:45 PM Go to last post
  4. Configuration via Protocol - load core from QSPI

    Started by simonkbrown, April 25th, 2016 04:45 AM
    • Replies: 0
    • Views: 46
    April 25th, 2016, 04:45 AM Go to last post
  5. altsyncram simulating, data changes on failing edge

    Started by Juzujka, April 22nd, 2016 04:30 AM
    • Replies: 2
    • Views: 91
    April 25th, 2016, 02:58 AM Go to last post
  6. half precision floating point in Aria 10

    Started by ggeorgak, April 24th, 2016 06:17 AM
    aria 10, floating point, half precision, quartus
    • Replies: 0
    • Views: 64
    April 24th, 2016, 06:17 AM Go to last post
    • Replies: 0
    • Views: 77
    April 22nd, 2016, 12:44 PM Go to last post
    • Replies: 0
    • Views: 66
    April 22nd, 2016, 08:22 AM Go to last post
  7. simulating Altera Reed-Solomon IP

    Started by Algorith, April 21st, 2016 01:14 PM
    altera ip, reed solomon, simulating
    • Replies: 0
    • Views: 58
    April 21st, 2016, 01:14 PM Go to last post
  8. Didital Down Converter

    Started by Alex_777, April 20th, 2016 04:23 AM
    • Replies: 0
    • Views: 80
    April 20th, 2016, 04:23 AM Go to last post
  9. pausing PCI HIP transactions with avalon mm waitrequest

    Started by YannnickLP, April 19th, 2016 11:53 PM
    avalon mm waitrequest, inner mechanism, pause writing, pci hip
    • Replies: 0
    • Views: 72
    April 19th, 2016, 11:53 PM Go to last post
  10. Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

    Started by dwh@ovro.caltech.edu, March 14th, 2012 09:55 AM
    11 Pages
    1 2 3 ... 11
    • Replies: 101
    • Views: 71,556
    April 15th, 2016, 03:08 PM Go to last post
  11. PCIe Avalon ST Multifunction Simulation

    Started by kaliprasad.kh, April 15th, 2016 05:54 AM
    • Replies: 0
    • Views: 86
    April 15th, 2016, 05:54 AM Go to last post
  12. SDI transmitter serial output problem

    Started by andruwkoo, April 15th, 2016 03:35 AM
    sdi
    • Replies: 0
    • Views: 76
    April 15th, 2016, 03:35 AM Go to last post
    • Replies: 1
    • Views: 89
    April 15th, 2016, 02:19 AM Go to last post
  13. Custom IP Simulation in ModelSim

    Started by manjurgl, April 12th, 2016 03:26 AM
    • Replies: 7
    • Views: 215
    April 13th, 2016, 06:51 AM Go to last post
  14. custom Avalon MM master questions.

    Started by kumanika, April 13th, 2016 02:12 AM
    • Replies: 2
    • Views: 144
    April 13th, 2016, 05:39 AM Go to last post
  15. DDR3 memory with Uniphy is SLOW

    Started by simonkbrown, April 12th, 2016 04:06 PM
    • Replies: 0
    • Views: 102
    April 12th, 2016, 04:06 PM Go to last post
    • Replies: 0
    • Views: 89
    April 11th, 2016, 06:06 AM Go to last post
  16. ALT PLL error

    Started by FPGA_guru011, April 11th, 2016 03:28 AM
    • Replies: 0
    • Views: 88
    April 11th, 2016, 03:28 AM Go to last post
  17. altera FFT

    Started by konstantino41, March 31st, 2016 03:17 AM
    • Replies: 7
    • Views: 312
    April 10th, 2016, 11:40 PM Go to last post
  18. Arria 10 External Memory Interface Invalid Data Width

    Started by MTBarnard, February 10th, 2016 08:16 AM
    address span externder, arria 10, data width, external memory interface
    • Replies: 1
    • Views: 246
    April 9th, 2016, 02:54 PM Go to last post
  19. Question Modular ADC - MAX10

    Started by marciomoura, April 8th, 2016 08:28 AM
    • Replies: 0
    • Views: 146
    April 8th, 2016, 08:28 AM Go to last post
  20. Cyclone V GT, Custom PHY IP Core

    Started by vfilos, April 7th, 2016 03:01 AM
    • Replies: 1
    • Views: 139
    April 7th, 2016, 05:06 AM Go to last post
  21. CIC IP Core in Quartus 15.1 for 5CSEBA5U23

    Started by mitya_kapl, March 21st, 2016 10:29 AM
    cic ip core, cyclone v, quartus 15.1
    • Replies: 5
    • Views: 263
    April 6th, 2016, 11:33 PM Go to last post
  22. Question Cannot generate rapid io ip core

    Started by cryshuan, April 5th, 2016 11:54 PM
    • Replies: 0
    • Views: 91
    April 5th, 2016, 11:54 PM Go to last post
  23. Deinterlacer problem

    Started by simonkbrown, April 4th, 2016 03:50 PM
    • Replies: 0
    • Views: 118
    April 4th, 2016, 03:50 PM Go to last post
  24. Turbo Megacore

    Started by nattyLev, April 3rd, 2016 12:31 AM
    turbo
    • Replies: 0
    • Views: 126
    April 3rd, 2016, 12:31 AM Go to last post
  25. Terasic PCIe example designs unable to decrypt files

    Started by tyx3gu, July 9th, 2015 02:56 PM
    pcie, quartus, terasic
    • Replies: 4
    • Views: 914
    April 1st, 2016, 04:05 PM Go to last post

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