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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. DE2 Quartus debounced circuit

    Started by kofinator, March 31st, 2007 10:55 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 99,645
    October 22nd, 2012, 12:09 AM Go to last post
  2. EP4CE6 Cyclone IVE FPGA regulator question

    Started by rcg14, October 19th, 2012 02:17 PM
    • Replies: 3
    • Views: 29,934
    October 20th, 2012, 08:52 AM Go to last post
  3. SR flipflop problem

    Started by hyeok1234, October 19th, 2012 07:00 PM
    • Replies: 3
    • Views: 31,614
    October 20th, 2012, 04:33 AM Go to last post
  4. DDR2 SDRAM uniPHY

    Started by cixenne, October 20th, 2012 03:42 AM
    • Replies: 0
    • Views: 34,019
    October 20th, 2012, 03:42 AM Go to last post
  5. LPM_Divide Megafunction Timing Issues

    Started by km25, October 16th, 2012 06:55 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 35,843
    October 19th, 2012, 06:41 AM Go to last post
  6. Cross sectional area of CYCLONE II EP2C35F672C6 device

    Started by Phani, October 18th, 2012 06:34 PM
    • Replies: 0
    • Views: 30,592
    October 18th, 2012, 06:34 PM Go to last post
  7. EPC16 Programs but Fails Verification

    Started by ghogerheiden, July 24th, 2012 11:50 AM
    • Replies: 1
    • Views: 30,744
    October 18th, 2012, 03:19 PM Go to last post
  8. CRC Compiler Inconsistent Results

    Started by chipslinger, October 18th, 2012 04:58 AM
    • Replies: 1
    • Views: 29,218
    October 18th, 2012, 05:37 AM Go to last post
  9. FPGA cyclone EP1C12Q240C8n

    Started by sampa2008das, October 12th, 2012 11:29 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 34,752
    October 18th, 2012, 02:12 AM Go to last post
  10. Arrow .coe file for FIR in xilinx?

    Started by azay, October 17th, 2012 08:31 PM
    • Replies: 1
    • Views: 31,963
    October 17th, 2012, 11:55 PM Go to last post
  11. "HREAD" is used but not declared"-Read text image data Error

    Started by greenQ, October 16th, 2012 08:13 AM
    • Replies: 9
    • Views: 36,777
    October 17th, 2012, 03:52 AM Go to last post
  12. Yet another Timing Constraints question

    Started by robinsonb5, October 15th, 2012 03:18 PM
    • Replies: 2
    • Views: 33,023
    October 16th, 2012, 11:18 AM Go to last post
  13. altera modelsim problem

    Started by amaltera, October 9th, 2012 04:39 AM
    • Replies: 1
    • Views: 29,024
    October 16th, 2012, 06:03 AM Go to last post
  14. create_generated_clock latency

    Started by vlsi_freak, October 15th, 2012 01:20 AM
    • Replies: 1
    • Views: 29,898
    October 16th, 2012, 03:15 AM Go to last post
  15. clock groups options

    Started by vlsi_freak, October 15th, 2012 05:06 AM
    • Replies: 1
    • Views: 29,601
    October 16th, 2012, 03:14 AM Go to last post
  16. band pass FIR filter and weird response

    Started by dejfson, October 15th, 2012 12:44 AM
    • Replies: 6
    • Views: 33,991
    October 15th, 2012, 11:02 PM Go to last post
  17. Pulse Width Modulation

    Started by rebk, October 14th, 2012 06:29 PM
    • Replies: 6
    • Views: 35,441
    October 15th, 2012, 05:14 PM Go to last post
  18. Power Estimator Discrepancy

    Started by clivewmwalker, October 15th, 2012 05:06 PM
    • Replies: 0
    • Views: 29,967
    October 15th, 2012, 05:06 PM Go to last post
  19. Simplest USB Implementation

    Started by adrian125, October 15th, 2012 10:58 AM
    • Replies: 0
    • Views: 32,207
    October 15th, 2012, 10:58 AM Go to last post
  20. Connect several ALTPLL on a input port signal

    Started by CORONAPAS, October 11th, 2012 11:49 PM
    • Replies: 2
    • Views: 30,473
    October 15th, 2012, 08:23 AM Go to last post
  21. Smile about the rx_signaldetect for sata

    Started by sbssdh, October 14th, 2012 11:31 PM
    • Replies: 0
    • Views: 30,400
    October 14th, 2012, 11:31 PM Go to last post
  22. Help: about PLL phase shift with stratix iv

    Started by tomlih, October 14th, 2012 06:19 PM
    • Replies: 1
    • Views: 31,823
    October 14th, 2012, 10:07 PM Go to last post
  23. Generating PWM in cyclon2

    Started by sameer123, April 6th, 2009 12:59 PM
    • Replies: 9
    • Views: 50,429
    October 14th, 2012, 09:29 PM Go to last post
  24. Red face Display color in Modelsim

    Started by notooth, October 4th, 2012 01:27 AM
    • Replies: 1
    • Views: 33,155
    October 13th, 2012, 12:21 PM Go to last post
  25. is it possible to download the training material PPT?

    Started by peterki, October 13th, 2012 10:00 AM
    • Replies: 0
    • Views: 29,799
    October 13th, 2012, 10:00 AM Go to last post
  26. the quarter sine LUT code

    Started by orao, October 9th, 2012 09:10 AM
    • Replies: 5
    • Views: 33,805
    October 13th, 2012, 09:44 AM Go to last post
  27. SOPC and beginbursttransfer

    Started by pinscore, September 10th, 2010 12:12 PM
    • Replies: 4
    • Views: 35,167
    October 12th, 2012, 03:57 PM Go to last post
  28. use OVL (Open Verification Library) with Quartus II VHDL

    Started by murillo, October 8th, 2012 06:06 AM
    • Replies: 8
    • Views: 31,277
    October 12th, 2012, 08:29 AM Go to last post
  29. help with a design example

    Started by mctnnn, October 12th, 2012 05:59 AM
    • Replies: 0
    • Views: 29,754
    October 12th, 2012, 05:59 AM Go to last post
  30. Crossing clock domains, PLL and TimeQuest

    Started by kolas, October 10th, 2012 01:10 PM
    • Replies: 4
    • Views: 39,303
    October 12th, 2012, 05:49 AM Go to last post

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