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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

    • Replies: 0
    • Views: 32,754
    August 15th, 2012, 07:26 AM Go to last post
  1. Alt_lvds and frame sync

    Started by mwb500, August 14th, 2012 01:01 PM
    • Replies: 0
    • Views: 31,906
    August 14th, 2012, 01:01 PM Go to last post
  2. Quartus to program Lattice LCMXO1200 CPLD via jtag

    Started by tapas2day, August 14th, 2012 09:02 AM
    • Replies: 1
    • Views: 33,985
    August 14th, 2012, 12:33 PM Go to last post
  3. Pausing target processor and other problems

    Started by skar, August 6th, 2012 05:16 AM
    • Replies: 2
    • Views: 30,080
    August 14th, 2012, 04:00 AM Go to last post
  4. using single wire as bus

    Started by educrania, August 13th, 2012 02:01 PM
    • Replies: 3
    • Views: 31,130
    August 14th, 2012, 12:55 AM Go to last post
  5. Arithmetics in VHDL

    Started by dvidorot, August 12th, 2012 01:47 AM
    • Replies: 4
    • Views: 32,969
    August 14th, 2012, 12:16 AM Go to last post
  6. Licensing Scheme, Please Clarify or Eliminate it.

    Started by volkswagenb, August 9th, 2012 11:29 AM
    • Replies: 8
    • Views: 31,009
    August 13th, 2012, 10:54 PM Go to last post
  7. Simple use of the VGA port and DE2 115

    Started by Pdoc, August 13th, 2012 04:48 PM
    • Replies: 0
    • Views: 27,100
    August 13th, 2012, 04:48 PM Go to last post
    • Replies: 1
    • Views: 32,239
    August 13th, 2012, 12:12 PM Go to last post
    • Replies: 0
    • Views: 27,399
    August 13th, 2012, 12:02 PM Go to last post
  8. elf2hex

    Started by guga, August 10th, 2012 08:20 AM
    • Replies: 3
    • Views: 34,138
    August 13th, 2012, 08:08 AM Go to last post
  9. Adding an algorithm

    Started by almemar, August 10th, 2012 06:12 PM
    • Replies: 1
    • Views: 31,662
    August 12th, 2012, 11:00 PM Go to last post
  10. system verilog "enum" and scope

    Started by srt_amol, August 8th, 2012 12:04 PM
    • Replies: 1
    • Views: 32,016
    August 10th, 2012, 03:16 PM Go to last post
  11. Arrow System ID issue

    Started by guga, July 25th, 2012 11:59 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 32,632
    August 9th, 2012, 11:33 PM Go to last post
  12. Angry Reduce total logic elements?

    Started by Azkan, August 9th, 2012 04:38 AM
    • Replies: 1
    • Views: 32,599
    August 9th, 2012, 10:20 AM Go to last post
  13. What is the difference..?

    Started by hyeok1234, August 8th, 2012 05:35 PM
    • Replies: 3
    • Views: 32,311
    August 9th, 2012, 04:47 AM Go to last post
  14. AD5620 DAC interface

    Started by glenn13, July 25th, 2012 12:51 AM
    • Replies: 8
    • Views: 31,082
    August 9th, 2012, 12:10 AM Go to last post
  15. Divide two 36 Bit values

    Started by phot, August 7th, 2012 11:53 PM
    • Replies: 5
    • Views: 32,636
    August 8th, 2012, 09:34 AM Go to last post
  16. Compilation Report

    Started by rob18767, August 7th, 2012 01:15 PM
    • Replies: 4
    • Views: 32,900
    August 8th, 2012, 05:04 AM Go to last post
    • Replies: 7
    • Views: 55,996
    August 8th, 2012, 04:54 AM Go to last post
  17. Probability successful in FPGA if done in modelsim!!

    Started by bacbac, August 2nd, 2012 02:53 PM
    • Replies: 5
    • Views: 31,043
    August 7th, 2012, 08:38 AM Go to last post
  18. Nios II BSP Editor

    Started by cuong.hong, August 6th, 2012 10:00 PM
    • Replies: 1
    • Views: 33,097
    August 6th, 2012, 11:48 PM Go to last post
  19. verilog error

    Started by sanjeev-parashar, August 4th, 2012 06:01 AM
    • Replies: 3
    • Views: 29,595
    August 6th, 2012, 11:30 PM Go to last post
    • Replies: 3
    • Views: 34,453
    August 6th, 2012, 10:11 PM Go to last post
  20. 哪位大神用过ad7401

    Started by kingyst, August 6th, 2012 07:56 PM
    • Replies: 0
    • Views: 30,694
    August 6th, 2012, 07:56 PM Go to last post
    • Replies: 4
    • Views: 44,926
    August 6th, 2012, 04:48 PM Go to last post
  21. Passing command line arguement in the .qsf file

    Started by ashishkaps, August 6th, 2012 05:53 AM
    • Replies: 0
    • Views: 32,838
    August 6th, 2012, 05:53 AM Go to last post
  22. Smile SDRAM Framebuffer with two asynchronous clocks

    Started by aact, July 25th, 2012 12:49 AM
    • Replies: 5
    • Views: 31,803
    August 6th, 2012, 12:37 AM Go to last post
  23. parallel lvds outputs

    Started by oscalcmen, August 3rd, 2012 03:17 PM
    • Replies: 4
    • Views: 30,046
    August 5th, 2012, 11:28 PM Go to last post
  24. verilog

    Started by sanjeev-parashar, August 4th, 2012 05:14 AM
    • Replies: 1
    • Views: 26,605
    August 5th, 2012, 07:29 PM Go to last post

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