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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Post ArriaIIGX dynamic reconfiguration analog control

    Started by okuyamamakoto, February 15th, 2017 03:03 AM
    • Replies: 0
    • Views: 53
    February 15th, 2017, 03:03 AM Go to last post
  2. SDRAM problem in SOPC builder.

    Started by lewy0701, September 10th, 2011 10:02 AM
    • Replies: 3
    • Views: 30,757
    February 15th, 2017, 01:46 AM Go to last post
  3. Using LVDS Clock in the DE0-Nano-SOC

    Started by mojcmos, February 14th, 2017 09:24 PM
    • Replies: 2
    • Views: 93
    February 15th, 2017, 01:46 AM Go to last post
  4. error : Cyclone V XCVR Illegal constraint of Channel PLL

    Started by hayder.h, February 13th, 2017 08:05 AM
    • Replies: 2
    • Views: 121
    February 15th, 2017, 12:53 AM Go to last post
  5. Post FPGA re-flashing and running application from parallel flash

    Started by zaks, February 13th, 2017 11:20 AM
    • Replies: 3
    • Views: 111
    February 14th, 2017, 08:00 PM Go to last post
  6. Question Stratix V Verilog Example

    Started by Tanash, February 14th, 2017 10:09 AM
    • Replies: 1
    • Views: 82
    February 14th, 2017, 11:19 AM Go to last post
  7. SDRAM read out of sync

    Started by SharpWeapon, February 2nd, 2017 09:50 PM
    de4, iord, iowr, pll, sdram
    • Replies: 5
    • Views: 236
    February 14th, 2017, 01:31 AM Go to last post
    • Replies: 0
    • Views: 67
    February 13th, 2017, 04:14 AM Go to last post
  8. Angry the ERROR 82 in the JTAG server

    Started by jameszum, July 3rd, 2008 11:43 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 65,144
    February 9th, 2017, 07:58 AM Go to last post
  9. Linker error when linking a large number of objects

    Started by Michael2017, February 9th, 2017 06:08 AM
    @file, arglist, linker
    • Replies: 0
    • Views: 63
    February 9th, 2017, 06:08 AM Go to last post
  10. Running a CYCLONE above its rated temperature

    Started by cc6g11, February 9th, 2017 01:37 AM
    • Replies: 2
    • Views: 134
    February 9th, 2017, 06:05 AM Go to last post
  11. Licensing Quartus II through remote license server

    Started by Jurke92, February 8th, 2017 01:26 AM
    • Replies: 2
    • Views: 126
    February 9th, 2017, 02:51 AM Go to last post
  12. EPCS128 Programming

    Started by HKH1367, February 6th, 2017 02:56 AM
    • Replies: 9
    • Views: 268
    February 9th, 2017, 02:17 AM Go to last post
  13. ALTLVDS_RX->LVDS serdes Link Training

    Started by ash80, December 28th, 2016 03:17 AM
    3 Pages
    1 2 3
    • Replies: 25
    • Views: 1,077
    February 8th, 2017, 06:30 PM Go to last post
  14. Programmer fails at 87% - SoCKit

    Started by matlabfft, November 13th, 2014 07:09 AM
    • Replies: 7
    • Views: 9,330
    February 8th, 2017, 02:27 PM Go to last post
  15. Quartus Lite wto program the DE1-SOC development board?

    Started by riverrock, February 8th, 2017 07:37 AM
    • Replies: 1
    • Views: 88
    February 8th, 2017, 11:47 AM Go to last post
  16. Simulator error

    Started by geoffop, January 25th, 2017 11:05 AM
    • Replies: 2
    • Views: 171
    February 8th, 2017, 08:16 AM Go to last post
  17. How to find a IP is free or requires license ?

    Started by rajeshrv_altera, February 6th, 2017 06:54 PM
    • Replies: 2
    • Views: 125
    February 7th, 2017, 04:48 PM Go to last post
  18. SignalTap autotriggers constantly without meeting conditions

    Started by jsag, February 7th, 2017 09:12 AM
    • Replies: 4
    • Views: 155
    February 7th, 2017, 12:24 PM Go to last post
  19. How redirect an analog signal to another pin.

    Started by Leonardo Castilho, February 6th, 2017 11:07 AM
    • Replies: 1
    • Views: 96
    February 7th, 2017, 03:51 AM Go to last post
  20. MAX V 1532 file

    Started by MisterVVC, February 7th, 2017 03:31 AM
    • Replies: 0
    • Views: 61
    February 7th, 2017, 03:31 AM Go to last post
  21. Max 10 CRC Error Detection Register Access

    Started by pslawinski, February 6th, 2017 12:24 PM
    • Replies: 1
    • Views: 85
    February 7th, 2017, 01:11 AM Go to last post
  22. Marvell 88EE1111 PHY tranciever MDIO reg configuration

    Started by jsag, January 25th, 2017 02:34 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 490
    February 6th, 2017, 12:50 PM Go to last post
  23. Nco fpga

    Started by HKH1367, February 2nd, 2017 10:46 PM
    • Replies: 0
    • Views: 122
    February 2nd, 2017, 10:46 PM Go to last post
  24. Post FPGA to Host PCIe Latency Calculation

    Started by vinayak.rh, February 2nd, 2017 01:09 AM
    latency, pcie, stratix v, timestamp
    • Replies: 0
    • Views: 105
    February 2nd, 2017, 01:09 AM Go to last post
  25. Question about boot NIOS from Micron N25Q flash

    Started by momoxinduo, January 30th, 2017 01:20 AM
    • Replies: 8
    • Views: 319
    February 1st, 2017, 10:02 AM Go to last post
  26. One JIC file to multiple FPGAs

    Started by Markus09, January 30th, 2017 05:49 AM
    jic, one image, quartus programmer, speedup
    • Replies: 5
    • Views: 201
    January 30th, 2017, 10:37 PM Go to last post
  27. the difference between a general clock inputs

    Started by yossiwf, January 29th, 2017 05:02 AM
    • Replies: 4
    • Views: 214
    January 30th, 2017, 06:11 AM Go to last post
  28. interfacing a pcie daughter card to development board

    Started by tmny2777, January 26th, 2017 12:09 PM
    • Replies: 6
    • Views: 265
    January 27th, 2017, 05:40 PM Go to last post
  29. How do I click to proceed during training videos?

    Started by apoorvad, January 27th, 2017 04:19 PM
    • Replies: 3
    • Views: 166
    January 27th, 2017, 05:30 PM Go to last post

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