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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Reconfig PLL in ALTMEMPHY

    Started by tuanna, December 14th, 2007 06:21 PM
    • Replies: 2
    • Views: 45,989
    December 26th, 2007, 06:46 PM Go to last post
  2. Refresh DDR2 in normal process!

    Started by tuanna, December 26th, 2007 06:40 PM
    • Replies: 0
    • Views: 44,009
    December 26th, 2007, 06:40 PM Go to last post
  3. preserve_hierarchy assignment

    Started by jefflieu, December 19th, 2007 11:18 PM
    • Replies: 3
    • Views: 44,832
    December 21st, 2007, 08:16 PM Go to last post
  4. bluetooth 2 IR converter for PS3 using MAX 7000 CPLD

    Started by Joe D, December 20th, 2007 09:00 AM
    • Replies: 0
    • Views: 60,847
    December 20th, 2007, 09:00 AM Go to last post
  5. Reconfig PLL in ALTMEMPHY

    Started by tuanna, December 17th, 2007 11:47 PM
    • Replies: 0
    • Views: 44,597
    December 17th, 2007, 11:47 PM Go to last post
  6. How can I get support of Altera if I use Web edition Quartus!

    Started by tuanna, December 13th, 2007 11:39 PM
    • Replies: 2
    • Views: 69,332
    December 17th, 2007, 06:46 PM Go to last post
  7. My one-cent question

    Started by jefflieu, December 12th, 2007 06:57 PM
    • Replies: 1
    • Views: 46,614
    December 15th, 2007, 06:39 PM Go to last post
  8. VHDL help, frequency Division

    Started by p00ndawg, November 29th, 2007 06:23 PM
    • Replies: 5
    • Views: 71,413
    December 15th, 2007, 02:46 AM Go to last post
  9. lpm_mult - no sum input

    Started by tns1, December 14th, 2007 07:38 AM
    • Replies: 1
    • Views: 44,781
    December 15th, 2007, 12:31 AM Go to last post
  10. something about ALTMEMPHY for DDR2 Interface!

    Started by tuanna, December 12th, 2007 07:08 PM
    • Replies: 0
    • Views: 55,681
    December 12th, 2007, 07:08 PM Go to last post
  11. Unhappy HELP: How to Use sopc to W/R two FLASH ?

    Started by hapyang, December 2nd, 2007 12:09 AM
    • Replies: 5
    • Views: 42,885
    December 10th, 2007, 01:16 AM Go to last post
  12. How to perform ddr sdram's performance?

    Started by syflx, December 7th, 2007 11:47 PM
    • Replies: 2
    • Views: 47,274
    December 9th, 2007, 11:59 PM Go to last post
  13. NIOS II and flash compatibility

    Started by fpgabuilder, August 15th, 2007 01:20 PM
    • Replies: 5
    • Views: 63,840
    December 9th, 2007, 10:21 PM Go to last post
  14. Help:Jtag configuration of Cyclone2

    Started by hapyang, December 5th, 2007 10:53 PM
    • Replies: 2
    • Views: 51,592
    December 7th, 2007, 03:22 PM Go to last post
  15. Using DDR SDRAM Controller

    Started by lasd, December 6th, 2007 12:09 AM
    • Replies: 2
    • Views: 51,782
    December 7th, 2007, 01:33 AM Go to last post
  16. Megafunction altparallel_flash_loader--what is this

    Started by Djoshi, November 19th, 2007 12:34 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 66,281
    December 6th, 2007, 07:14 AM Go to last post
  17. Interfacing DDR SDRAM with Stratix II

    Started by svasan, November 3rd, 2007 03:38 PM
    • Replies: 1
    • Views: 53,507
    December 6th, 2007, 04:58 AM Go to last post
  18. ALTMEMPHY problem and simulation issue

    Started by tuanna, December 6th, 2007 03:00 AM
    • Replies: 0
    • Views: 48,050
    December 6th, 2007, 03:00 AM Go to last post
  19. Post Regarding Cyclone FPGA and Top boot Flash memory configuration

    Started by niti.dl, December 6th, 2007 12:11 AM
    • Replies: 0
    • Views: 55,399
    December 6th, 2007, 12:11 AM Go to last post
  20. altmemphy problem!

    Started by tuanna, December 3rd, 2007 07:13 PM
    • Replies: 0
    • Views: 50,444
    December 3rd, 2007, 07:13 PM Go to last post
    • Replies: 2
    • Views: 47,164
    December 2nd, 2007, 03:18 AM Go to last post
  21. AP configuration and flash usage

    Started by lael, November 29th, 2007 05:22 AM
    • Replies: 1
    • Views: 46,613
    November 29th, 2007, 07:58 PM Go to last post
  22. Can conditional builds be performed in VHDL?

    Started by wolson, November 14th, 2007 05:58 AM
    • Replies: 5
    • Views: 68,458
    November 29th, 2007, 09:47 AM Go to last post
  23. Regarding PLL design

    Started by pradeepkumar, November 29th, 2007 01:27 AM
    • Replies: 1
    • Views: 49,107
    November 29th, 2007, 06:19 AM Go to last post
  24. high speed pulse generation

    Started by tns1, November 8th, 2007 09:30 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 70,247
    November 28th, 2007, 10:29 PM Go to last post
  25. Cyclone 3 board acting up.

    Started by Evenstar, November 27th, 2007 02:44 PM
    • Replies: 1
    • Views: 52,327
    November 28th, 2007, 11:42 AM Go to last post
  26. Verilog to VHDL

    Started by neptunus, November 22nd, 2007 10:40 AM
    • Replies: 2
    • Views: 54,801
    November 26th, 2007, 05:11 AM Go to last post
  27. Avalon-MM master? in SOPC for a FLASH mem

    Started by Djoshi, November 20th, 2007 07:04 AM
    • Replies: 7
    • Views: 62,335
    November 23rd, 2007, 07:36 PM Go to last post
  28. Probelm when write/read DDR2 memory

    Started by bigyellow, November 22nd, 2007 05:06 AM
    • Replies: 0
    • Views: 53,958
    November 22nd, 2007, 05:06 AM Go to last post
  29. Cyclone III and FLash --need some help people

    Started by Djoshi, November 19th, 2007 10:53 AM
    • Replies: 0
    • Views: 50,326
    November 19th, 2007, 10:53 AM Go to last post

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