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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Help for SOPC Builder - simple DDR2 design

    Started by Francoisb, February 6th, 2009 02:01 AM
    • Replies: 0
    • Views: 49,440
    February 6th, 2009, 02:01 AM Go to last post
  2. Verilog FSM not working on FPGA

    Started by itsallmoto, February 3rd, 2009 09:19 AM
    • Replies: 9
    • Views: 56,398
    February 5th, 2009, 08:48 AM Go to last post
  3. Avalon ST bridge information

    Started by fgriffon, February 3rd, 2009 05:03 AM
    • Replies: 1
    • Views: 45,814
    February 4th, 2009, 12:28 AM Go to last post
  4. libraries for VHDL

    Started by varunvj86, February 2nd, 2009 08:37 PM
    • Replies: 2
    • Views: 48,075
    February 3rd, 2009, 10:04 PM Go to last post
  5. How to interface PC and FPGA through USB 2.0

    Started by ujala, February 3rd, 2009 07:12 AM
    • Replies: 1
    • Views: 41,769
    February 3rd, 2009, 09:19 AM Go to last post
    • Replies: 7
    • Views: 47,949
    February 3rd, 2009, 05:52 AM Go to last post
  6. Isochronous mode USB with NIOS

    Started by suitcase, February 3rd, 2009 05:31 AM
    • Replies: 0
    • Views: 47,326
    February 3rd, 2009, 05:31 AM Go to last post
  7. error in compiling VHDL CODE

    Started by varunvj86, February 2nd, 2009 01:11 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 85,842
    February 2nd, 2009, 10:48 PM Go to last post
  8. Red face mutex core!!

    Started by Forever, January 29th, 2009 01:25 AM
    • Replies: 0
    • Views: 48,335
    January 29th, 2009, 01:25 AM Go to last post
  9. Multiplex Megacore

    Started by clericnmf, January 28th, 2009 07:38 AM
    • Replies: 2
    • Views: 48,947
    January 28th, 2009, 08:09 AM Go to last post
  10. Question Very simple question, first time using Verilog here...

    Started by ST4DMAN, January 28th, 2009 02:05 AM
    • Replies: 2
    • Views: 56,911
    January 28th, 2009, 08:04 AM Go to last post
  11. NCO Frequency modualtion

    Started by clericnmf, January 27th, 2009 01:52 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 60,121
    January 28th, 2009, 07:36 AM Go to last post
  12. Post About "alt_flash_open_dev" and CFI table

    Started by otis, August 18th, 2008 12:31 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 62,923
    January 28th, 2009, 06:30 AM Go to last post
  13. asi output clock

    Started by teodoralexandra, January 21st, 2009 01:21 AM
    • Replies: 1
    • Views: 45,923
    January 28th, 2009, 12:43 AM Go to last post
  14. Problem editing component SOPC

    Started by pieman02, January 27th, 2009 12:06 AM
    • Replies: 3
    • Views: 44,215
    January 28th, 2009, 12:09 AM Go to last post
  15. Problems using command-line interface

    Started by busfault, January 27th, 2009 01:40 PM
    • Replies: 2
    • Views: 52,811
    January 27th, 2009, 02:20 PM Go to last post
  16. 32-bit SSRAM must have byteenable for Nios II?

    Started by fffzzz, September 2nd, 2008 05:36 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 67,743
    January 27th, 2009, 03:45 AM Go to last post
  17. Question problem access meories !!

    Started by Forever, January 26th, 2009 03:28 AM
    • Replies: 3
    • Views: 44,445
    January 27th, 2009, 02:29 AM Go to last post
  18. Transmit 2 bits of 1MHz (modulation)

    Started by roboticsBCN, January 26th, 2009 08:27 AM
    • Replies: 3
    • Views: 49,702
    January 26th, 2009, 02:41 PM Go to last post
  19. Can not dowload the code into my Altera

    Started by ecenus, January 19th, 2009 10:18 AM
    • Replies: 9
    • Views: 46,818
    January 24th, 2009, 02:21 AM Go to last post
  20. linear to logarithmic conversion

    Started by gargamit, January 19th, 2009 09:54 AM
    • Replies: 6
    • Views: 47,100
    January 23rd, 2009, 07:49 AM Go to last post
  21. embedded signals in modelsim

    Started by washburn, January 19th, 2009 12:07 PM
    • Replies: 5
    • Views: 47,295
    January 23rd, 2009, 07:32 AM Go to last post
  22. need more info about Altera courses

    Started by Remiadamov, January 20th, 2009 08:09 AM
    • Replies: 1
    • Views: 42,376
    January 22nd, 2009, 10:58 AM Go to last post
  23. Question delay for a Sinusoid

    Started by ragaja1, January 15th, 2009 06:55 AM
    • Replies: 6
    • Views: 47,694
    January 22nd, 2009, 09:04 AM Go to last post
  24. How to hold data in a register

    Started by john7, January 22nd, 2009 04:39 AM
    • Replies: 2
    • Views: 44,724
    January 22nd, 2009, 07:19 AM Go to last post
  25. FrameBuffer/ memory arbitration problem

    Started by Nadeem, January 22nd, 2009 03:21 AM
    • Replies: 0
    • Views: 44,988
    January 22nd, 2009, 03:21 AM Go to last post
  26. Signal has no source

    Started by john7, January 21st, 2009 02:57 AM
    • Replies: 4
    • Views: 49,815
    January 21st, 2009, 04:18 AM Go to last post
  27. VHDL architecture

    Started by Dvido, January 15th, 2009 01:43 AM
    • Replies: 4
    • Views: 58,756
    January 19th, 2009, 08:48 AM Go to last post
  28. Pin problem about tri_state_bridge

    Started by liu11nan, January 13th, 2009 08:14 AM
    • Replies: 9
    • Views: 44,259
    January 18th, 2009, 05:52 AM Go to last post
  29. how to increase frequency

    Started by gargamit, January 14th, 2009 08:57 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 79,278
    January 18th, 2009, 05:20 AM Go to last post

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