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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. how to find the APIs of the ip in nios?

    Started by qd0090, September 9th, 2014 08:48 PM
    • Replies: 2
    • Views: 12,159
    September 10th, 2014, 04:40 AM Go to last post
    • Replies: 0
    • Views: 12,389
    September 9th, 2014, 01:18 PM Go to last post
  2. Image Processing on FPGAs

    Started by fammy88, September 6th, 2014 02:02 AM
    • Replies: 1
    • Views: 11,783
    September 6th, 2014, 04:02 AM Go to last post
  3. Getting the System Time in VHDL

    Started by runvs99, March 30th, 2012 03:21 PM
    • Replies: 3
    • Views: 31,387
    September 6th, 2014, 01:14 AM Go to last post
  4. Stratix 1 to Arria V conversion

    Started by jcloidt, September 4th, 2014 09:11 AM
    • Replies: 2
    • Views: 13,072
    September 4th, 2014, 01:27 PM Go to last post
  5. Problem configuring Arria II GX in AS mode with EPCS128

    Started by lethenstrom, September 3rd, 2014 01:36 PM
    .jic, configuration, epcs
    • Replies: 1
    • Views: 13,253
    September 4th, 2014, 05:38 AM Go to last post
    • Replies: 0
    • Views: 12,819
    September 4th, 2014, 12:56 AM Go to last post
  6. Quartus Web version vs Subscription version

    Started by PierreC, September 3rd, 2014 06:23 AM
    • Replies: 3
    • Views: 12,714
    September 3rd, 2014, 07:39 AM Go to last post
  7. Invalid Signal Splitter Error

    Started by RogerPone, September 3rd, 2014 02:17 AM
    • Replies: 0
    • Views: 12,457
    September 3rd, 2014, 02:17 AM Go to last post
  8. Cyclone III Reset with unrelated HV pulses

    Started by ABierman1986, August 28th, 2014 08:40 AM
    • Replies: 2
    • Views: 12,992
    September 2nd, 2014, 12:46 AM Go to last post
  9. Help with slim model

    Started by dozerunfv, September 1st, 2014 08:48 PM
    • Replies: 1
    • Views: 12,373
    September 1st, 2014, 10:57 PM Go to last post
  10. Question Emulated LVDS

    Started by yon116, August 16th, 2009 04:29 AM
    • Replies: 7
    • Views: 44,812
    August 31st, 2014, 01:03 AM Go to last post
    • Replies: 1
    • Views: 13,379
    August 29th, 2014, 07:13 AM Go to last post
  11. Scatter-gather DMA IP simulation

    Started by li_polaris, August 21st, 2014 05:56 PM
    • Replies: 4
    • Views: 12,970
    August 28th, 2014, 10:25 PM Go to last post
  12. How do you import a .vqm from Synplify?

    Started by swimteam, August 27th, 2014 11:51 AM
    • Replies: 1
    • Views: 13,336
    August 28th, 2014, 12:54 PM Go to last post
  13. simulation with modelsim after quartus II vhdl design

    Started by santib77, August 27th, 2014 07:19 AM
    • Replies: 3
    • Views: 13,186
    August 28th, 2014, 07:14 AM Go to last post
  14. Multiplexing a clock signal in Cyclon III.

    Started by yairs, August 17th, 2014 03:19 AM
    • Replies: 1
    • Views: 13,646
    August 27th, 2014, 04:46 AM Go to last post
  15. Allegro Design Entry HDL Symbol for Cyclone IV

    Started by EMSpectrum, August 22nd, 2014 06:09 AM
    allegro design entry hdl, concept, cyclone iv, symbol
    • Replies: 3
    • Views: 14,033
    August 27th, 2014, 04:42 AM Go to last post
  16. backward compatibility of Quartus 13.1 - 64 bit

    Started by asanjasima, August 25th, 2014 10:59 PM
    764 bit, backward compatibility, quartus 12.1, quartus13.1
    • Replies: 3
    • Views: 13,602
    August 25th, 2014, 11:47 PM Go to last post
  17. Unhappy Indirect configuration

    Started by temi42, August 25th, 2014 05:07 AM
    as 4x, cyclone v, indirect, msel
    • Replies: 1
    • Views: 11,791
    August 25th, 2014, 10:13 AM Go to last post
    • Replies: 1
    • Views: 11,781
    August 25th, 2014, 08:03 AM Go to last post
  18. Error (114005): Can't find database file ... .(0).cnf.cdb.wrk

    Started by gavyus, October 14th, 2013 07:12 AM
    • Replies: 4
    • Views: 29,751
    August 25th, 2014, 07:37 AM Go to last post
  19. system.h not reloading

    Started by astdom, March 6th, 2014 12:59 AM
    • Replies: 3
    • Views: 16,965
    August 22nd, 2014, 05:50 AM Go to last post
  20. Single address Avalon MM slave

    Started by vdkeybus, August 22nd, 2014 12:33 AM
    avalon mm, qsys, sopc builder
    • Replies: 5
    • Views: 13,793
    August 22nd, 2014, 05:49 AM Go to last post
  21. DDR2 HPCII control signal always low

    Started by RogerPone, August 22nd, 2014 02:13 AM
    • Replies: 0
    • Views: 12,122
    August 22nd, 2014, 02:13 AM Go to last post
    • Replies: 2
    • Views: 16,614
    August 21st, 2014, 12:48 PM Go to last post
  22. Optical FPGAs

    Started by evita, August 20th, 2014 08:48 AM
    • Replies: 4
    • Views: 13,309
    August 21st, 2014, 08:09 AM Go to last post
  23. DDR2 TimeQuest

    Started by RogerPone, August 20th, 2014 05:17 AM
    • Replies: 0
    • Views: 12,464
    August 20th, 2014, 05:17 AM Go to last post
  24. Verifying Sampled Data in FPGA ?

    Started by matlabfft, August 19th, 2014 11:31 AM
    • Replies: 1
    • Views: 12,518
    August 19th, 2014, 12:10 PM Go to last post
  25. Loading .bdf file into ModelSim

    Started by LukeAtJBU, August 15th, 2014 12:17 PM
    .bdf, modelsim, schematic, waveform
    • Replies: 1
    • Views: 13,860
    August 15th, 2014, 12:28 PM Go to last post

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