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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. SD card multiple read

    Started by phd.taha, Yesterday 10:57 AM
    • Replies: 3
    • Views: 104
    Today, 12:24 AM Go to last post
  2. Exclamation Cyclone III Configuration Problem

    Started by dcallahanjr, July 21st, 2017 12:21 PM
    • Replies: 4
    • Views: 201
    Yesterday, 06:26 AM Go to last post
    • Replies: 1
    • Views: 130
    Yesterday, 01:42 AM Go to last post
    • Replies: 3
    • Views: 99
    Yesterday, 12:24 AM Go to last post
  3. Looking for used Bemicro CV A9

    Started by ricardjc, April 26th, 2017 06:01 AM
    bemicro
    • Replies: 1
    • Views: 665
    July 24th, 2017, 04:54 PM Go to last post
  4. Part Number for 10-Pin Male Header for JTAG connection

    Started by Akanimo, July 24th, 2017 01:25 PM
    • Replies: 1
    • Views: 85
    July 24th, 2017, 01:30 PM Go to last post
  5. Power Management in Cyclone V SOC

    Started by Rabiammal, July 19th, 2017 02:51 AM
    • Replies: 2
    • Views: 210
    July 22nd, 2017, 04:50 AM Go to last post
  6. Basic example of lpm_counter1 disabled when in overflow

    Started by cosmos, July 21st, 2017 09:11 AM
    • Replies: 2
    • Views: 183
    July 21st, 2017, 11:29 AM Go to last post
  7. Question basic example Avalon MM bus

    Started by sxmg92, July 20th, 2017 03:18 PM
    • Replies: 3
    • Views: 178
    July 21st, 2017, 10:35 AM Go to last post
    • Replies: 1
    • Views: 135
    July 21st, 2017, 06:49 AM Go to last post
  8. Altera MAX EPM7256AQI208

    Started by Craig Test, July 21st, 2017 02:54 AM
    • Replies: 0
    • Views: 114
    July 21st, 2017, 02:54 AM Go to last post
    • Replies: 0
    • Views: 84
    July 20th, 2017, 09:00 PM Go to last post
  9. A++ compiler

    Started by akira, March 21st, 2017 02:56 AM
    • Replies: 3
    • Views: 901
    July 20th, 2017, 08:38 AM Go to last post
  10. About the .edf file

    Started by darlingsun, April 20th, 2015 09:02 PM
    .edf
    • Replies: 1
    • Views: 1,200
    July 19th, 2017, 01:38 PM Go to last post
  11. Cyclone IV / Cyclone V : PCI 3.0-V

    Started by peio, July 18th, 2017 12:00 AM
    cyclone iv, cyclone v, pci, pci bus
    • Replies: 3
    • Views: 269
    July 19th, 2017, 06:48 AM Go to last post
    • Replies: 2
    • Views: 295
    July 18th, 2017, 07:19 AM Go to last post
  12. ALTLVDS_RX Compensating for Data Skew

    Started by gj_leeson, July 17th, 2017 12:05 PM
    • Replies: 0
    • Views: 152
    July 17th, 2017, 12:05 PM Go to last post
  13. Question Maser address range conflict

    Started by Hugo, July 17th, 2017 01:10 AM
    • Replies: 0
    • Views: 166
    July 17th, 2017, 01:10 AM Go to last post
  14. How shoud I start to FPGA?

    Started by Zek_De, July 13th, 2017 11:49 AM
    • Replies: 8
    • Views: 591
    July 14th, 2017, 09:34 AM Go to last post
  15. Cmd line - how to get started?

    Started by jcw, July 12th, 2017 02:37 PM
    • Replies: 2
    • Views: 311
    July 13th, 2017, 02:48 AM Go to last post
  16. Post How to implement TCP/IP Client basing on NiosII

    Started by yangroot98071, July 12th, 2017 11:17 PM
    • Replies: 0
    • Views: 232
    July 12th, 2017, 11:17 PM Go to last post
  17. Smile Avalon Streaming simple example

    Started by aidin62, May 19th, 2010 07:56 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 50,192
    July 12th, 2017, 11:30 AM Go to last post
  18. help with Altera DE4 Development and Education Board

    Started by mburko, July 11th, 2017 04:51 PM
    altera, board, de4, development, education
    • Replies: 1
    • Views: 244
    July 12th, 2017, 06:36 AM Go to last post
  19. DDR3 Testing

    Started by shmueld, July 12th, 2017 01:22 AM
    • Replies: 0
    • Views: 222
    July 12th, 2017, 01:22 AM Go to last post
    • Replies: 9
    • Views: 608
    July 11th, 2017, 11:56 PM Go to last post
  20. High Level Synthesis

    Started by BKN, July 10th, 2017 02:32 PM
    • Replies: 6
    • Views: 518
    July 11th, 2017, 02:15 AM Go to last post
  21. clock freqency of opencl module in de5a-net board

    Started by stevenyytan, July 9th, 2017 11:07 PM
    • Replies: 0
    • Views: 265
    July 9th, 2017, 11:07 PM Go to last post
  22. Angry verify failed on onchip-memory

    Started by ZS10060201, July 6th, 2017 07:05 PM
    verify failed
    • Replies: 1
    • Views: 375
    July 9th, 2017, 04:55 PM Go to last post
  23. Uninitialized value of a signal in vhdl

    Started by mahmood, July 9th, 2017 11:16 AM
    • Replies: 1
    • Views: 298
    July 9th, 2017, 11:42 AM Go to last post
    • Replies: 0
    • Views: 252
    July 8th, 2017, 09:42 PM Go to last post

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