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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. USB Blaster for DE1 board

    Started by Zeel, Yesterday 07:02 PM
    usb blaster, windows 8.1
    • Replies: 5
    • Views: 130
    Today, 02:21 AM Go to last post
  2. Cyclone V Configuration Devices

    Started by gj_leeson, October 14th, 2017 10:12 AM
    • Replies: 8
    • Views: 322
    Today, 01:50 AM Go to last post
  3. Using Byte Blaster Rev. C with FTDI232RL breakout board

    Started by XAUI, October 16th, 2017 05:48 PM
    • Replies: 2
    • Views: 158
    Today, 01:22 AM Go to last post
  4. Avalon Memory Mapped pipelined slave writes

    Started by steve_stl_01, Yesterday 08:10 AM
    avalon-mm, pipeline, slave
    • Replies: 1
    • Views: 85
    Yesterday, 09:08 AM Go to last post
  5. Question PCIE Pinout doubts and Problems Cyclone V

    Started by sxmg92, October 14th, 2017 11:29 AM
    pcie, pinouts
    • Replies: 1
    • Views: 213
    October 18th, 2017, 09:52 PM Go to last post
  6. Program EPM7064 to match EPS464

    Started by jrippin, October 16th, 2017 01:24 PM
    epm7064, eps464
    • Replies: 4
    • Views: 252
    October 17th, 2017, 11:03 PM Go to last post
  7. nested loop error in OpenCL hardware run

    Started by Lancerchiang, October 17th, 2017 02:31 AM
    hardware, loop, opencl, quartus, simulation
    • Replies: 3
    • Views: 191
    October 17th, 2017, 07:59 PM Go to last post
  8. SODIMM RAM interfacing with FPGA

    Started by subhrajitmitra, October 17th, 2017 07:36 AM
    • Replies: 0
    • Views: 113
    October 17th, 2017, 07:36 AM Go to last post
    • Replies: 0
    • Views: 131
    October 16th, 2017, 02:00 PM Go to last post
  9. Implementation of VHDL program on FPGA

    Started by berkoka, October 15th, 2017 09:21 AM
    • Replies: 8
    • Views: 293
    October 16th, 2017, 12:10 PM Go to last post
  10. EPCS Discontinuation, looking for replacement.

    Started by BhavaniT, September 22nd, 2017 07:42 AM
    • Replies: 5
    • Views: 798
    October 16th, 2017, 01:29 AM Go to last post
    • Replies: 2
    • Views: 383
    October 15th, 2017, 07:21 PM Go to last post
  11. Cyclone V Transceiver Backplane Support

    Started by joe306, October 4th, 2017 02:11 PM
    • Replies: 2
    • Views: 368
    October 15th, 2017, 07:18 PM Go to last post
  12. Building Quartus16.1 files on Quartus 16.0

    Started by jeebujacob, October 9th, 2017 02:30 AM
    quartus, timingclosure
    • Replies: 5
    • Views: 389
    October 15th, 2017, 07:14 PM Go to last post
  13. Lightbulb Programming cyclone III & IV using a custom USB Blaster

    Started by DavidR, October 27th, 2015 06:08 AM
    blaster, configuration, cyclone, ftdi
    • Replies: 7
    • Views: 3,137
    October 14th, 2017, 11:42 PM Go to last post
  14. Footprint for UBGA 324 pin package

    Started by rod@ariradesign.com, October 11th, 2017 04:30 PM
    • Replies: 6
    • Views: 348
    October 14th, 2017, 03:04 AM Go to last post
  15. Post Noise decoupling

    Started by shipra7993, October 13th, 2017 11:10 PM
    • Replies: 0
    • Views: 168
    October 13th, 2017, 11:10 PM Go to last post
  16. Exclamation Hardware run result does no match with simulation

    Started by Lancerchiang, October 13th, 2017 12:55 AM
    hardware, opencl, quartus, simulation
    • Replies: 2
    • Views: 261
    October 13th, 2017, 08:34 AM Go to last post
  17. Cyclone V E Instantiating Multiple ASMI Blocks

    Started by polson, October 11th, 2017 07:46 AM
    • Replies: 0
    • Views: 217
    October 11th, 2017, 07:46 AM Go to last post
  18. Cannot generate cof file - Quartus Prime Lite V17 (595)

    Started by Cluso99, October 9th, 2017 09:35 PM
    • Replies: 2
    • Views: 286
    October 10th, 2017, 02:27 PM Go to last post
  19. Cyclone V SoC Development Kit

    Started by th_altera_forum, August 18th, 2017 06:10 PM
    • Replies: 5
    • Views: 979
    October 10th, 2017, 12:53 PM Go to last post
  20. Angry Cannot login properly to myAltera

    Started by qu1j0t3, October 7th, 2017 02:21 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 1,601
    October 9th, 2017, 10:38 PM Go to last post
  21. Teraisc DE0-CV (Cyclone V) programming error

    Started by yileku, October 8th, 2017 10:25 AM
    • Replies: 1
    • Views: 248
    October 9th, 2017, 10:10 AM Go to last post
  22. Post sof file not updated

    Started by mrbenzalot, October 9th, 2017 05:58 AM
    • Replies: 0
    • Views: 211
    October 9th, 2017, 05:58 AM Go to last post
  23. project compilation is taking forever to finish

    Started by Lancerchiang, October 8th, 2017 05:45 PM
    compilation, opencl, quartus, synthesis
    • Replies: 3
    • Views: 321
    October 9th, 2017, 12:55 AM Go to last post
  24. Quartus II and Altera Usb Blaster

    Started by mustafayilmaz, October 8th, 2017 09:50 AM
    • Replies: 1
    • Views: 243
    October 8th, 2017, 11:45 AM Go to last post
  25. Video memory scheme?

    Started by Pickwick, October 6th, 2017 09:27 AM
    • Replies: 1
    • Views: 312
    October 6th, 2017, 02:07 PM Go to last post
  26. DE0-Nano-SoC: How HPS(ARM) recognizes f2h_irq0 or f2h_irq1 interrupts from FPGA

    Started by sebar, January 16th, 2016 09:41 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 4,001
    October 6th, 2017, 09:30 AM Go to last post
    • Replies: 1
    • Views: 306
    October 6th, 2017, 05:02 AM Go to last post
  27. Can not reprogram the FPGA/JTAG does not respond

    Started by tamzidul, September 29th, 2017 11:31 AM
    • Replies: 2
    • Views: 435
    October 3rd, 2017, 12:48 AM Go to last post

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