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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 2
    • Views: 204
    Yesterday, 09:19 PM Go to last post
  1. DECA max 10 dev kit not detected

    Started by josbouten, September 11th, 2017 03:08 PM
    deca max 10 dev kit, hardware detection
    • Replies: 1
    • Views: 442
    Yesterday, 03:04 PM Go to last post
  2. Cyclone 10 GX EMIF PLL clock input

    Started by Y0tsuya, December 14th, 2017 07:29 PM
    • Replies: 0
    • Views: 144
    December 14th, 2017, 07:29 PM Go to last post
  3. IOPLL Source Synchronous Compensation Issue? -- Arria 10

    Started by mvinskus, December 14th, 2017 11:02 AM
    arria 10, iopll, source synchronous
    • Replies: 1
    • Views: 244
    December 14th, 2017, 11:55 AM Go to last post
  4. Driving DCLK pin after FPGA configuration

    Started by raja1, December 14th, 2017 05:58 AM
    • Replies: 0
    • Views: 130
    December 14th, 2017, 05:58 AM Go to last post
  5. Using Cypress FX3 as device for Passive Serial

    Started by RickyThomson, December 4th, 2017 02:44 AM
    • Replies: 7
    • Views: 443
    December 14th, 2017, 12:08 AM Go to last post
  6. Looking for 125C Automotive EPCS or EPCQ (replacement) version

    Started by edgar85, October 30th, 2017 06:34 AM
    • Replies: 2
    • Views: 530
    December 13th, 2017, 09:48 AM Go to last post
  7. Please help with PLL

    Started by skliarovartem, December 13th, 2017 04:28 AM
    • Replies: 3
    • Views: 223
    December 13th, 2017, 09:25 AM Go to last post
  8. Arria 10: Packing 2 Multipliers per DSP

    Started by systom, December 12th, 2017 11:44 AM
    arria, dsp, integer, multiplier
    • Replies: 2
    • Views: 204
    December 12th, 2017, 12:03 PM Go to last post
  9. Cyclone V: How to access AS EPCS if booted from HPS?

    Started by Sorgelig, December 12th, 2017 04:09 AM
    • Replies: 1
    • Views: 195
    December 12th, 2017, 07:37 AM Go to last post
  10. Arria 10 multiplier speed

    Started by eazycnc, December 11th, 2017 12:24 AM
    • Replies: 6
    • Views: 272
    December 12th, 2017, 07:05 AM Go to last post
  11. MAX 10 Modular ADC core problem with reserved pins

    Started by ilynxy, December 11th, 2017 03:31 AM
    • Replies: 2
    • Views: 256
    December 11th, 2017, 11:28 PM Go to last post
  12. Help with cyclone iv (ep4ce6e22c8n)

    Started by kurof, December 11th, 2017 03:10 PM
    • Replies: 3
    • Views: 240
    December 11th, 2017, 09:13 PM Go to last post
    • Replies: 3
    • Views: 324
    December 11th, 2017, 07:48 PM Go to last post
  13. How to stream video (and process) into FPGA

    Started by dman, November 21st, 2017 03:08 AM
    2 Pages
    1 2
    camera, ddr, fpga, image, image processing
    • Replies: 15
    • Views: 1,289
    December 11th, 2017, 10:02 AM Go to last post
  14. Cyclone 10 LP Clock input and data in different banks

    Started by Shareef, December 8th, 2017 08:27 AM
    cyclone 10 lp; clock
    • Replies: 1
    • Views: 294
    December 11th, 2017, 05:02 AM Go to last post
  15. Arria V tranceiver clocking

    Started by alcotel, December 7th, 2017 02:05 AM
    • Replies: 2
    • Views: 349
    December 10th, 2017, 02:28 AM Go to last post
  16. Question ALTDDIO_OUT for clock output of chip

    Started by Hendrik2k1, December 6th, 2017 06:26 AM
    • Replies: 7
    • Views: 473
    December 9th, 2017, 05:48 AM Go to last post
  17. [VHDL] Compilation Order

    Started by dmitryl, December 7th, 2017 05:27 PM
    • Replies: 8
    • Views: 474
    December 8th, 2017, 08:01 AM Go to last post
  18. JTAG timing constraints

    Started by daniel@3t.nl, September 25th, 2017 03:48 AM
    2 Pages
    1 2
    • Replies: 17
    • Views: 1,496
    December 7th, 2017, 02:18 PM Go to last post
  19. MAX 10 FPGA Program File

    Started by shevagol777, December 5th, 2017 04:54 AM
    • Replies: 7
    • Views: 493
    December 7th, 2017, 06:12 AM Go to last post
  20. Cyclone 5 mismatch between VCCPD and VCCIO

    Started by sherif123456, December 5th, 2017 03:47 AM
    • Replies: 6
    • Views: 458
    December 6th, 2017, 09:48 PM Go to last post
  21. MAX 10 - Storing configuration in its internal FLASH

    Started by Lurkers, November 23rd, 2017 03:29 PM
    • Replies: 3
    • Views: 408
    December 6th, 2017, 05:59 PM Go to last post
  22. EP20K300EFC672-2X EOl

    Started by dheinz, November 30th, 2017 09:21 AM
    fpga, nsn, obsolete, replacement
    • Replies: 1
    • Views: 309
    December 6th, 2017, 04:18 PM Go to last post
  23. Cyclone IV IBIS Model

    Started by nicx82, December 5th, 2017 12:12 AM
    • Replies: 1
    • Views: 271
    December 5th, 2017, 06:54 PM Go to last post
  24. MAX 10 FPGA power-on/configuration error

    Started by plewis, July 5th, 2017 05:18 AM
    configuration, fpga, max10
    • Replies: 6
    • Views: 1,454
    December 5th, 2017, 05:25 PM Go to last post
  25. Cyclone V PLL : "Normal" mode compensation is not working.

    Started by lundril, December 5th, 2017 09:11 AM
    • Replies: 0
    • Views: 212
    December 5th, 2017, 09:11 AM Go to last post
  26. interfacing to epcq256 through fpga

    Started by alexander14, November 20th, 2017 10:53 AM
    • Replies: 9
    • Views: 865
    December 5th, 2017, 09:03 AM Go to last post
  27. EPCS4SI8N > EPCQ4ASI8N For Old Cyclone FPGA

    Started by mflorczak, December 4th, 2017 08:41 AM
    • Replies: 3
    • Views: 319
    December 5th, 2017, 08:17 AM Go to last post
  28. MAX 10, using LVDS differential clock input.

    Started by emotal, December 4th, 2017 01:17 PM
    • Replies: 2
    • Views: 317
    December 5th, 2017, 08:16 AM Go to last post

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