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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Exponential function in vhdl

    Started by Nidhi, August 25th, 2016 11:38 PM
    • Replies: 8
    • Views: 172
    Yesterday, 11:57 PM Go to last post
    • Replies: 0
    • Views: 81
    Yesterday, 08:17 AM Go to last post
    • Replies: 3
    • Views: 91
    Yesterday, 01:42 AM Go to last post
  2. Altium Component 10M50DC F484

    Started by jerome_h, August 25th, 2016 03:46 AM
    10m50dc f484, f256, footprint, package, symbol
    • Replies: 1
    • Views: 61
    August 25th, 2016, 03:41 PM Go to last post
  3. How to start with MAX10 evaluation board?

    Started by matic_o, August 19th, 2016 08:34 AM
    max10
    • Replies: 2
    • Views: 50
    August 25th, 2016, 03:38 PM Go to last post
  4. MLAB physical size for Stratix V

    Started by geiguren, August 25th, 2016 06:00 AM
    • Replies: 1
    • Views: 60
    August 25th, 2016, 03:33 PM Go to last post
  5. Stratix IV FPGA transceiver for the optical switching

    Started by xiongyl, August 25th, 2016 01:15 PM
    • Replies: 0
    • Views: 43
    August 25th, 2016, 01:15 PM Go to last post
  6. MAX10 ADC doesn't start during power on

    Started by kattice, April 5th, 2016 10:18 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 736
    August 24th, 2016, 01:26 PM Go to last post
  7. min/max trace delays

    Started by vlrean, August 23rd, 2016 05:59 AM
    • Replies: 3
    • Views: 91
    August 24th, 2016, 05:19 AM Go to last post
  8. FPGA to Optical NoC

    Started by nizdom, August 22nd, 2016 10:58 PM
    • Replies: 2
    • Views: 84
    August 23rd, 2016, 06:50 AM Go to last post
    • Replies: 1
    • Views: 94
    August 22nd, 2016, 05:46 AM Go to last post
  9. FPGA Cyclone V power from single DC/DC chip

    Started by sherif123, August 20th, 2016 04:04 AM
    • Replies: 3
    • Views: 125
    August 20th, 2016, 09:57 PM Go to last post
  10. Angry About altera Cyclone V package library

    Started by jone_990, August 18th, 2016 09:24 PM
    cyclone v package library
    • Replies: 6
    • Views: 154
    August 19th, 2016, 05:46 PM Go to last post
  11. Quartus 16.0.0 no pof generated

    Started by gj_leeson, August 19th, 2016 12:31 PM
    • Replies: 1
    • Views: 103
    August 19th, 2016, 01:05 PM Go to last post
  12. Lightbulb EPM240T100C5 not work reading data from RAM

    Started by dimo41, August 15th, 2016 11:51 PM
    • Replies: 1
    • Views: 113
    August 18th, 2016, 01:17 AM Go to last post
    • Replies: 2
    • Views: 149
    August 17th, 2016, 11:56 PM Go to last post
  13. how do i speed up place&route timing in cyclone V

    Started by jeffsheen, August 16th, 2016 05:41 PM
    • Replies: 4
    • Views: 150
    August 17th, 2016, 01:43 PM Go to last post
  14. How to calculate parameters for reconfigure a pll

    Started by nicx82, October 7th, 2011 02:01 AM
    • Replies: 7
    • Views: 42,239
    August 17th, 2016, 11:06 AM Go to last post
  15. Infer Large Multiplier in Stratix IV

    Started by Tricky, August 5th, 2016 07:19 AM
    • Replies: 1
    • Views: 117
    August 17th, 2016, 10:34 AM Go to last post
  16. Question MAX10 pin too close to PLL clock

    Started by DoctornoUA, May 11th, 2016 09:52 AM
    • Replies: 8
    • Views: 538
    August 16th, 2016, 03:47 AM Go to last post
  17. how do I generate 32k clock from cyclone V pll

    Started by jeffsheen, August 11th, 2016 04:03 PM
    2 Pages
    1 2
    • Replies: 18
    • Views: 344
    August 15th, 2016, 04:35 PM Go to last post
    • Replies: 4
    • Views: 128
    August 13th, 2016, 02:48 PM Go to last post
  18. Fault Injection on Stratix V via JTAG interface

    Started by andradx, August 10th, 2016 05:23 AM
    crc, emr, fault injection, jtag, seu
    • Replies: 1
    • Views: 99
    August 12th, 2016, 07:49 AM Go to last post
  19. Availability PLD Applications CPCI10K-PROD

    Started by mygnom, August 11th, 2016 11:47 PM
    • Replies: 0
    • Views: 79
    August 11th, 2016, 11:47 PM Go to last post
  20. PI controller in VHDL

    Started by maha.eg, December 12th, 2011 04:59 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 107,617
    August 10th, 2016, 05:32 PM Go to last post
  21. UniPHY LPDDR2 Controller Memory Clock Rate

    Started by gj_leeson, August 10th, 2016 08:10 AM
    • Replies: 0
    • Views: 74
    August 10th, 2016, 08:10 AM Go to last post
  22. Max 10 yield problem

    Started by bretpollack, August 9th, 2016 08:07 AM
    • Replies: 1
    • Views: 121
    August 9th, 2016, 10:55 AM Go to last post
    • Replies: 0
    • Views: 105
    August 7th, 2016, 10:08 PM Go to last post
    • Replies: 5
    • Views: 42,376
    August 5th, 2016, 07:51 PM Go to last post
  23. Cyclone III + EPCS4 + UART remote upgrade

    Started by zhangyi17, July 21st, 2016 06:24 AM
    • Replies: 3
    • Views: 242
    August 5th, 2016, 02:22 PM Go to last post

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