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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 0
    • Views: 29
    Yesterday, 01:14 PM Go to last post
  1. Question MAX10 dual boot, NIOS2 boot from UFM. Not booting.

    Started by Eggi, June 23rd, 2016 12:29 AM
    dual boot, max10, nios2, qsys, ufm
    • Replies: 1
    • Views: 71
    Yesterday, 09:33 AM Go to last post
    • Replies: 4
    • Views: 130
    June 23rd, 2016, 08:50 AM Go to last post
  2. invert clock at output pin in DDR3 uniphy controller

    Started by ingdxdy, June 21st, 2016 09:24 PM
    • Replies: 4
    • Views: 80
    June 23rd, 2016, 06:00 AM Go to last post
  3. MAX7000 GCLRn dedicated pin

    Started by carloc, June 16th, 2016 12:32 AM
    • Replies: 2
    • Views: 76
    June 23rd, 2016, 01:11 AM Go to last post
  4. Configure MAX10 CPLD using remote micro CPU

    Started by Anton Khmelenko, June 21st, 2016 11:36 PM
    max 10 jtag configure
    • Replies: 3
    • Views: 76
    June 23rd, 2016, 12:31 AM Go to last post
  5. ROM Initialization, Max 10 device 10M02

    Started by synchronous, June 17th, 2016 03:15 PM
    10m02, error 16031, max 10
    • Replies: 2
    • Views: 101
    June 22nd, 2016, 01:37 AM Go to last post
  6. cyglone 5 gt interface for ads5263

    Started by thieulam, June 15th, 2016 02:28 AM
    • Replies: 1
    • Views: 62
    June 21st, 2016, 10:17 PM Go to last post
  7. MAX10 onchip flash with quartus prime light

    Started by dambsst, November 21st, 2015 01:30 AM
    flash quartus prime
    • Replies: 1
    • Views: 730
    June 21st, 2016, 12:01 PM Go to last post
  8. Question Cyclone V partial reconfiguration support

    Started by intel, June 15th, 2016 10:07 PM
    • Replies: 4
    • Views: 130
    June 20th, 2016, 07:37 PM Go to last post
  9. Cyclone V and Security

    Started by Don_Camillo, June 14th, 2016 03:21 AM
    • Replies: 3
    • Views: 106
    June 20th, 2016, 07:21 PM Go to last post
  10. Regarding POF file format

    Started by JackHsu, June 18th, 2016 07:56 AM
    • Replies: 2
    • Views: 101
    June 20th, 2016, 10:37 AM Go to last post
  11. Camera Link - FPGA I/O protection

    Started by sasushi1, July 5th, 2012 11:02 PM
    • Replies: 5
    • Views: 31,491
    June 20th, 2016, 10:33 AM Go to last post
    • Replies: 3
    • Views: 95
    June 20th, 2016, 07:41 AM Go to last post
  12. Altera 1517 Lid and Die questions

    Started by Divergence, June 6th, 2016 07:46 AM
    • Replies: 1
    • Views: 104
    June 19th, 2016, 11:46 PM Go to last post
  13. Fast data tranfer to PC

    Started by ctzof, June 17th, 2016 05:47 AM
    • Replies: 8
    • Views: 167
    June 19th, 2016, 11:44 PM Go to last post
  14. Red face Big IC delay timing

    Started by RADAMAHER, June 8th, 2016 11:57 AM
    • Replies: 2
    • Views: 121
    June 19th, 2016, 11:36 PM Go to last post
  15. Alternative JTAG Programing

    Started by iulianvalentin, June 19th, 2016 10:15 AM
    • Replies: 0
    • Views: 70
    June 19th, 2016, 10:15 AM Go to last post
  16. Availability of MAX 10 devices in 144-EQFP packages?

    Started by shaynal, June 15th, 2016 10:35 AM
    • Replies: 2
    • Views: 100
    June 17th, 2016, 07:24 PM Go to last post
  17. simulating crc error using ederror_inject jtag instrucrion

    Started by n.sara, June 17th, 2016 02:04 AM
    • Replies: 0
    • Views: 63
    June 17th, 2016, 02:04 AM Go to last post
  18. Error: Peak virtual memory: 255 megabytes (Quartus)

    Started by Javier09, June 16th, 2016 08:56 AM
    • Replies: 1
    • Views: 80
    June 16th, 2016, 12:21 PM Go to last post
  19. MAX 10 Pin Questions

    Started by shaynal, April 27th, 2016 09:37 PM
    • Replies: 2
    • Views: 227
    June 15th, 2016, 10:00 AM Go to last post
  20. FPGA + Camera iamge sensors

    Started by sherif123, April 23rd, 2016 07:40 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 451
    June 15th, 2016, 02:39 AM Go to last post
  21. Programmatic Reset/Reconfig of Cyclone FPGA

    Started by altusrvan1, June 10th, 2016 01:43 PM
    internal, reset
    • Replies: 4
    • Views: 171
    June 14th, 2016, 10:37 AM Go to last post
  22. Selecting Pages in a JIC file

    Started by srisid14, June 11th, 2016 10:31 AM
    • Replies: 1
    • Views: 102
    June 14th, 2016, 02:56 AM Go to last post
  23. How to interface FFT core with I/O

    Started by mws000, June 13th, 2016 11:34 AM
    • Replies: 0
    • Views: 80
    June 13th, 2016, 11:34 AM Go to last post
  24. Hard Copy ASIC for MAX 10 FPGA Design

    Started by b.ritesh, June 12th, 2016 09:54 PM
    • Replies: 1
    • Views: 83
    June 13th, 2016, 07:02 AM Go to last post
  25. Resize function not working

    Started by swarnava9, June 12th, 2016 08:51 AM
    resize
    • Replies: 3
    • Views: 187
    June 12th, 2016, 12:50 PM Go to last post
    • Replies: 0
    • Views: 91
    June 11th, 2016, 10:47 PM Go to last post
  26. all bins on tristate

    Started by teslatower, June 11th, 2016 09:51 AM
    cpld, maxv
    • Replies: 3
    • Views: 141
    June 11th, 2016, 02:43 PM Go to last post

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