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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Question Active serial configuration problem

    Started by EvgenyMuryshkin, May 28th, 2016 02:49 AM
    • Replies: 3
    • Views: 88
    Yesterday, 03:43 PM Go to last post
  2. Measuring clock from DE0-Nano on scope

    Started by nettek, May 19th, 2016 05:28 AM
    • Replies: 2
    • Views: 143
    May 28th, 2016, 06:09 AM Go to last post
  3. Cyclone V Local or Remote Configuration

    Started by hm83, April 23rd, 2014 03:20 AM
    • Replies: 2
    • Views: 15,455
    May 27th, 2016, 07:22 AM Go to last post
  4. Question What is the EPM7128 data retention time?

    Started by 1009760140, May 26th, 2016 12:21 AM
    • Replies: 4
    • Views: 117
    May 27th, 2016, 02:23 AM Go to last post
    • Replies: 2
    • Views: 104
    May 27th, 2016, 12:24 AM Go to last post
  5. Implementing an asynchronous counter in a FPGA

    Started by dams0622, May 23rd, 2016 01:37 AM
    • Replies: 9
    • Views: 217
    May 24th, 2016, 07:54 AM Go to last post
    • Replies: 3
    • Views: 159
    May 24th, 2016, 07:38 AM Go to last post
  6. Question u-boot fpga driver to handel configuration

    Started by mondher, May 24th, 2016 01:50 AM
    cyclone v, driver, external processor, ps configuration, u-boot
    • Replies: 0
    • Views: 58
    May 24th, 2016, 01:50 AM Go to last post
  7. Question Cyclone V flashing LEDs and clock (Verilog)

    Started by pmamatsis, May 22nd, 2016 05:56 AM
    clock, cyclone v, megafunction, pll
    • Replies: 4
    • Views: 151
    May 24th, 2016, 01:26 AM Go to last post
  8. Speed optimization

    Started by a4atmel, May 21st, 2016 06:18 AM
    • Replies: 2
    • Views: 131
    May 23rd, 2016, 03:09 AM Go to last post
    • Replies: 2
    • Views: 30,466
    May 22nd, 2016, 10:35 PM Go to last post
  9. Soft-Serdes for LVDS Issues

    Started by Jerry, May 22nd, 2016 08:29 PM
    • Replies: 0
    • Views: 66
    May 22nd, 2016, 08:29 PM Go to last post
  10. How to find largest value and its position in memory array?

    Started by GOH WEN SHIN, February 25th, 2014 11:29 PM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 21,503
    May 21st, 2016, 09:05 PM Go to last post
    • Replies: 2
    • Views: 157
    May 21st, 2016, 06:15 AM Go to last post
  11. CyClone IV PLL Dynamic Phase Shifting Probem

    Started by gj_leeson, May 16th, 2016 07:25 AM
    • Replies: 2
    • Views: 130
    May 20th, 2016, 12:54 AM Go to last post
  12. Question Demo Program THDB - ADA HSMC Board

    Started by Laplatrix, May 9th, 2016 10:52 PM
    • Replies: 3
    • Views: 158
    May 18th, 2016, 06:38 AM Go to last post
  13. How to close timing with Negative Setup Slack

    Started by jeebujacob, May 13th, 2016 12:07 AM
    • Replies: 8
    • Views: 242
    May 18th, 2016, 01:26 AM Go to last post
  14. Powering FPGA During Programming

    Started by newtham, May 12th, 2016 10:29 AM
    blaster, jtag, power, programming, vcc
    • Replies: 4
    • Views: 180
    May 17th, 2016, 09:48 AM Go to last post
  15. DSP Chain length of Cyclone V

    Started by filter.digital, May 17th, 2016 03:58 AM
    dsp chain
    • Replies: 0
    • Views: 92
    May 17th, 2016, 03:58 AM Go to last post
  16. Clock data recovery

    Started by nd89, May 15th, 2016 01:05 PM
    cdr, manchester encoding, pll
    • Replies: 3
    • Views: 139
    May 17th, 2016, 03:42 AM Go to last post
  17. loop must end 5000 iteration error

    Started by arunkupradhan, March 27th, 2010 09:57 AM
    • Replies: 4
    • Views: 42,173
    May 15th, 2016, 06:32 AM Go to last post
  18. CAM(Content Addressable Memory) into QDRII+ / DDR3

    Started by b.ritesh, May 12th, 2016 12:08 AM
    • Replies: 1
    • Views: 125
    May 13th, 2016, 10:44 PM Go to last post
  19. Cyclone V GX using all 6 transceivers in both directions

    Started by tkhansen@bksv.com, October 8th, 2015 06:10 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 1,846
    May 13th, 2016, 01:30 AM Go to last post
  20. Max 10 DDR Memory Interface Support

    Started by abaylis, May 10th, 2016 10:18 AM
    • Replies: 4
    • Views: 196
    May 11th, 2016, 09:44 PM Go to last post
  21. External Memory without BGA?

    Started by crabtack, May 6th, 2016 03:17 AM
    • Replies: 6
    • Views: 266
    May 11th, 2016, 09:39 PM Go to last post
  22. Modelsim error

    Started by NIDHI PANDA, May 7th, 2016 09:10 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 466
    May 11th, 2016, 10:29 AM Go to last post
  23. Question MAX10 pin too close to PLL clock

    Started by DoctornoUA, May 11th, 2016 09:52 AM
    • Replies: 0
    • Views: 57
    May 11th, 2016, 09:52 AM Go to last post
  24. Help with DE1 D5M camera and VGA

    Started by nizdom, May 10th, 2016 09:18 PM
    • Replies: 0
    • Views: 100
    May 10th, 2016, 09:18 PM Go to last post
    • Replies: 0
    • Views: 94
    May 10th, 2016, 03:22 PM Go to last post
  25. Seek programming assistance.

    Started by evalon, May 8th, 2016 01:15 AM
    assistance, fpga, paid, programming, streaming
    • Replies: 1
    • Views: 147
    May 10th, 2016, 06:16 AM Go to last post

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