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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 0
    • Views: 1
    Today, 06:21 AM Go to last post
  1. Setting VCC on MAX 10

    Started by mhubel, Yesterday 07:20 PM
    • Replies: 2
    • Views: 45
    Today, 05:29 AM Go to last post
  2. Unhappy Configuration Cyclone V 5CEBA9F23C8N

    Started by HKH1367, January 21st, 2017 11:49 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 157
    Today, 04:23 AM Go to last post
  3. Question Remote System Update with Max 10 10M16

    Started by KonradH, January 20th, 2017 12:26 AM
    dualconfiguration, max10, qsys, rsu
    • Replies: 7
    • Views: 122
    Today, 03:45 AM Go to last post
  4. JTAG pin sharing problem

    Started by qdkdcq, March 31st, 2016 01:24 AM
    max10 jtag sharing
    • Replies: 3
    • Views: 776
    Today, 03:06 AM Go to last post
  5. JTAG pin sharing problem

    Started by qdkdcq, March 31st, 2016 02:49 AM
    max10 jtag sharing pin
    • Replies: 2
    • Views: 509
    Today, 03:02 AM Go to last post
  6. Multistage pipelined multiplexer

    Started by shaiko, Yesterday 11:36 AM
    • Replies: 3
    • Views: 61
    Yesterday, 04:23 PM Go to last post
    • Replies: 2
    • Views: 85
    January 20th, 2017, 07:01 AM Go to last post
  7. Read program from the CPLD Altera MAX7128S

    Started by plml73, January 17th, 2017 10:42 PM
    • Replies: 6
    • Views: 148
    January 19th, 2017, 10:23 AM Go to last post
  8. SDC for ALTCLKCTRL

    Started by shaiko, January 15th, 2017 11:55 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 326
    January 19th, 2017, 07:52 AM Go to last post
  9. Do you think the MAX10 will fit my ocxo application?

    Started by Terje, January 17th, 2017 10:30 AM
    • Replies: 3
    • Views: 115
    January 18th, 2017, 07:58 PM Go to last post
  10. Error (15684)

    Started by fabf, September 20th, 2016 12:14 PM
    • Replies: 2
    • Views: 375
    January 18th, 2017, 12:45 PM Go to last post
  11. DE0-Nano: Want to learn how to use

    Started by tdg8934, January 17th, 2017 11:26 AM
    • Replies: 3
    • Views: 118
    January 18th, 2017, 11:33 AM Go to last post
  12. cyclone iii problem with ddr sdram pin

    Started by pangsong, March 26th, 2009 11:34 PM
    • Replies: 7
    • Views: 49,436
    January 15th, 2017, 10:48 PM Go to last post
  13. Max10 PCB Layout - Unused Pins

    Started by newtham, April 5th, 2016 01:36 PM
    2 Pages
    1 2
    layout, max10, pcb
    • Replies: 13
    • Views: 1,501
    January 15th, 2017, 05:23 PM Go to last post
  14. NEED HELP FOR DE0's UART

    Started by bomobye, December 17th, 2016 06:49 AM
    • Replies: 2
    • Views: 233
    January 13th, 2017, 07:24 AM Go to last post
  15. MAX10: JTAG sharing not working -- how to erase fw-image?

    Started by luigi70, January 12th, 2017 10:57 AM
    erase firmware, jtag sharing, jtagen, max10, nconfig
    • Replies: 1
    • Views: 95
    January 13th, 2017, 04:30 AM Go to last post
  16. ALTPLL vs ALTPLL_RECONFIG

    Started by dmitryl_amarel, January 5th, 2017 12:35 AM
    • Replies: 5
    • Views: 225
    January 13th, 2017, 03:08 AM Go to last post
  17. new to NIOS II. Need help for my requirement.

    Started by thunderbolt, January 6th, 2017 05:53 PM
    • Replies: 2
    • Views: 161
    January 9th, 2017, 10:47 PM Go to last post
  18. ALTCLKCTRL vs PLL with 2 reference clocks

    Started by shaiko, January 8th, 2017 11:34 PM
    • Replies: 3
    • Views: 124
    January 9th, 2017, 04:53 AM Go to last post
  19. max10 dual image + dual hex for nios

    Started by Andy Right, July 24th, 2015 09:58 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 2,289
    January 6th, 2017, 03:36 PM Go to last post
  20. EPF10k10 configuration time?

    Started by Mux, September 30th, 2012 08:28 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 35,384
    January 6th, 2017, 03:14 PM Go to last post
  21. Gated Clock + Clock MUX-> what primitives to use?

    Started by dmitryl_amarel, January 5th, 2017 05:51 AM
    • Replies: 2
    • Views: 153
    January 6th, 2017, 11:55 AM Go to last post
  22. Adding + reconfig of ALTPLL to the Project

    Started by dmitryl_amarel, January 5th, 2017 04:51 AM
    • Replies: 1
    • Views: 106
    January 6th, 2017, 02:37 AM Go to last post
  23. Altera DE2-115 (Cyclone IV) VS. Altera Cyclone V SoC

    Started by eLg, January 4th, 2017 05:38 PM
    fpga soc
    • Replies: 2
    • Views: 167
    January 5th, 2017, 06:30 PM Go to last post
  24. Question Fractional pll reconfig on cyclone v - share with mux

    Started by foft, January 5th, 2017 01:22 PM
    cyclonev, fpll, pll, reconfig
    • Replies: 0
    • Views: 78
    January 5th, 2017, 01:22 PM Go to last post
  25. Cyclone 5 maximum size DDR3

    Started by sherif123, January 1st, 2017 05:23 AM
    • Replies: 3
    • Views: 191
    January 5th, 2017, 03:15 AM Go to last post
    • Replies: 2
    • Views: 196
    January 5th, 2017, 01:13 AM Go to last post
  26. moving average filter - unkown signal issue

    Started by RobertLyle, January 4th, 2017 05:05 AM
    • Replies: 5
    • Views: 218
    January 5th, 2017, 12:20 AM Go to last post
  27. Unhappy Scrolling Text - 7 Segment Display on DE0-CV

    Started by Komotonoto, January 3rd, 2017 05:05 PM
    • Replies: 2
    • Views: 148
    January 4th, 2017, 08:02 AM Go to last post

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