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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Transceiver passthrough in Cyclone V

    Started by csebastian, February 16th, 2017 08:27 AM
    cyclone v, transceiver
    • Replies: 6
    • Views: 155
    Today, 12:02 PM Go to last post
  2. Clocking MAX10 and ADC at same 125 MHz frequency

    Started by JacobJ, Yesterday 10:14 PM
    • Replies: 3
    • Views: 51
    Today, 06:12 AM Go to last post
  3. Post arria10 fitter conflict for pin assignment

    Started by liu_uestc, February 7th, 2017 05:54 AM
    arrio 10, mac phy, pin assignment
    • Replies: 3
    • Views: 114
    Today, 01:57 AM Go to last post
  4. Change device compilation is unsuccessful

    Started by nbk, Today 01:24 AM
    • Replies: 0
    • Views: 25
    Today, 01:24 AM Go to last post
  5. D flip flop trouble

    Started by volvogv, Yesterday 06:35 PM
    • Replies: 0
    • Views: 23
    Yesterday, 06:35 PM Go to last post
  6. Configure 3.3V outputs on MAX7000

    Started by stevendt, February 20th, 2017 03:52 PM
    • Replies: 4
    • Views: 94
    Yesterday, 11:18 AM Go to last post
    • Replies: 0
    • Views: 46
    February 21st, 2017, 11:31 PM Go to last post
  7. Can't close timing on one clock domain

    Started by hcalla93, February 17th, 2017 03:12 AM
    • Replies: 6
    • Views: 206
    February 21st, 2017, 08:16 AM Go to last post
  8. Zero-delay PLL dividing frequency by 2

    Started by csebastian, February 21st, 2017 06:36 AM
    cyclone v, fpll, zero-delay
    • Replies: 0
    • Views: 47
    February 21st, 2017, 06:36 AM Go to last post
  9. Dual-port access avalon memory simulation problem

    Started by rozsatib, February 20th, 2017 04:15 AM
    • Replies: 3
    • Views: 86
    February 21st, 2017, 06:07 AM Go to last post
  10. Post Reloading User Flash Memory without recompiling

    Started by keithaf, February 15th, 2017 10:37 AM
    • Replies: 1
    • Views: 94
    February 19th, 2017, 06:03 AM Go to last post
  11. Multipath timing constraints not giving expected results

    Started by m_brej, February 14th, 2017 04:16 AM
    • Replies: 7
    • Views: 232
    February 17th, 2017, 03:52 PM Go to last post
    • Replies: 5
    • Views: 154
    February 17th, 2017, 07:38 AM Go to last post
  12. very slow simulation of Arria 10 LVDS SERDES

    Started by jens, February 17th, 2017 02:53 AM
    • Replies: 2
    • Views: 84
    February 17th, 2017, 04:35 AM Go to last post
  13. Max 10 Open Drain in analog banks

    Started by thebhef, February 15th, 2017 12:09 AM
    analog, bank1a, io bank, max10, open-drain
    • Replies: 5
    • Views: 135
    February 17th, 2017, 01:08 AM Go to last post
  14. Stratix 10 H-tile PLL performance

    Started by chenzhu99, February 16th, 2017 04:39 PM
    transceiver pll
    • Replies: 0
    • Views: 65
    February 16th, 2017, 04:39 PM Go to last post
  15. How to implement DSP operations

    Started by rozsatib, February 16th, 2017 02:04 AM
    • Replies: 1
    • Views: 103
    February 16th, 2017, 04:58 AM Go to last post
  16. sd card emulation

    Started by e97, February 16th, 2017 12:06 AM
    • Replies: 0
    • Views: 76
    February 16th, 2017, 12:06 AM Go to last post
  17. Alternative command to set_case_analysis or set_false_path ?

    Started by Gaetan, February 14th, 2017 08:04 AM
    fpga, sdc, time quest, timing constraints
    • Replies: 2
    • Views: 98
    February 15th, 2017, 07:37 AM Go to last post
  18. Post PLL error in BeMicro Max10 FPGA Evaluation Board

    Started by musthafavakeri, January 4th, 2016 10:27 PM
    avalon altpll, bemicro, max10
    • Replies: 2
    • Views: 886
    February 14th, 2017, 11:00 AM Go to last post
  19. MAX 10 Modular ADC TSD

    Started by eyarg, November 27th, 2016 05:30 AM
    10m50daf256i7g, adc, max 10, temperature, tsd
    • Replies: 1
    • Views: 258
    February 14th, 2017, 03:32 AM Go to last post
  20. Question Epm570t100i5n - cpld ser

    Started by Legendrykrish, February 8th, 2017 05:15 AM
    • Replies: 1
    • Views: 91
    February 13th, 2017, 10:18 PM Go to last post
  21. EQFP144 footprint for Allegro

    Started by Javiwolf, February 13th, 2017 05:54 AM
    eqfp144, footprint, max10
    • Replies: 2
    • Views: 108
    February 13th, 2017, 10:14 PM Go to last post
  22. Help with datasheet.

    Started by Nitofex, February 11th, 2017 09:48 AM
    • Replies: 1
    • Views: 79
    February 13th, 2017, 03:24 PM Go to last post
    • Replies: 1
    • Views: 90
    February 13th, 2017, 03:06 PM Go to last post
  23. SignalTap-II -> "instance not found" error

    Started by dmitryl, October 27th, 2015 12:58 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 2,396
    February 13th, 2017, 06:49 AM Go to last post
  24. MAX10 10M50SCE144C8G trouble on programming

    Started by rromano001, February 5th, 2017 02:03 PM
    • Replies: 5
    • Views: 189
    February 12th, 2017, 04:19 AM Go to last post
  25. Lightbulb Hot-plug VCCIO changing on MAX10 (10M16SC)

    Started by Neruo, February 10th, 2017 05:22 AM
    change, fpga, ios, max10, vccio
    • Replies: 0
    • Views: 55
    February 10th, 2017, 05:22 AM Go to last post
  26. Constraining source syncronous output

    Started by Rookie2017, February 8th, 2017 12:02 PM
    delay, sdc, source, syncronous, timing
    • Replies: 6
    • Views: 270
    February 9th, 2017, 11:19 AM Go to last post
    • Replies: 3
    • Views: 128
    February 9th, 2017, 05:54 AM Go to last post

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