Page 1 of 204 1231151101 ... LastLast
Threads 1 to 30 of 6097

Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 2
    • Views: 160
    Yesterday, 09:38 AM Go to last post
  1. MSEL driving

    Started by kstk, May 14th, 2018 09:41 AM
    • Replies: 4
    • Views: 312
    Yesterday, 09:24 AM Go to last post
  2. Question Setting up PCIe Connection Cyclone V

    Started by milleral, April 12th, 2018 02:23 PM
    cyclone v, fpga, pcie
    • Replies: 7
    • Views: 775
    May 22nd, 2018, 11:20 PM Go to last post
    • Replies: 2
    • Views: 1,249
    May 22nd, 2018, 11:14 AM Go to last post
  3. DDR4 connection to Arria10

    Started by kstk, May 22nd, 2018 02:03 AM
    • Replies: 1
    • Views: 110
    May 22nd, 2018, 11:02 AM Go to last post
  4. Progress FAILED !!! on the programmer.

    Started by ocy, May 18th, 2018 12:29 AM
    • Replies: 8
    • Views: 391
    May 22nd, 2018, 03:30 AM Go to last post
  5. FSM POR/Reset State on Cyclone 10 LP

    Started by christnp, May 21st, 2018 06:02 PM
    • Replies: 1
    • Views: 146
    May 22nd, 2018, 02:56 AM Go to last post
  6. Need pin diagram Stratix V (5SGSKF4013LNAC)

    Started by saint78, May 21st, 2018 12:59 PM
    • Replies: 1
    • Views: 142
    May 21st, 2018, 01:30 PM Go to last post
  7. migration from EPCQ to EPCQ-A

    Started by tomatoma, May 3rd, 2018 01:54 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 786
    May 19th, 2018, 11:10 AM Go to last post
  8. Cyclone IV GX transceiver eval board ethernet issue

    Started by bachimanchi, March 30th, 2018 06:02 AM
    • Replies: 1
    • Views: 399
    May 18th, 2018, 06:28 AM Go to last post
  9. PTP 1588 on Cyclone V

    Started by hardwareStudent, July 1st, 2014 11:18 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 19,911
    May 17th, 2018, 10:50 PM Go to last post
    • Replies: 3
    • Views: 347
    May 17th, 2018, 03:11 PM Go to last post
  10. Question Can not program MAX7000

    Started by gwhelbig, May 16th, 2018 02:01 PM
    jtag, max7000, pof, programming
    • Replies: 3
    • Views: 329
    May 17th, 2018, 08:10 AM Go to last post
  11. drive the input pins during the power-up/down sequence

    Started by kstk, May 14th, 2018 08:42 AM
    • Replies: 2
    • Views: 321
    May 15th, 2018, 04:31 AM Go to last post
  12. EPCQ-L Obsolescence

    Started by kstk, May 13th, 2018 12:14 PM
    • Replies: 3
    • Views: 334
    May 14th, 2018, 07:46 PM Go to last post
    • Replies: 1
    • Views: 258
    May 14th, 2018, 12:07 PM Go to last post
  13. FPGA Power Measurement

    Started by majdaldin, May 14th, 2018 11:46 AM
    fpga, measurement, power
    • Replies: 0
    • Views: 246
    May 14th, 2018, 11:46 AM Go to last post
  14. EP3C40F780C6 PCIe implementation

    Started by Sathya, May 14th, 2018 08:55 AM
    ep3c40f780c6, pcie
    • Replies: 0
    • Views: 234
    May 14th, 2018, 08:55 AM Go to last post
  15. Standart quartz oscillator

    Started by demsp, May 13th, 2018 11:27 PM
    • Replies: 2
    • Views: 252
    May 14th, 2018, 08:37 AM Go to last post
  16. Don't work DDIO input registers in Arria 10

    Started by andruwkoo, May 14th, 2018 04:21 AM
    altddio, arria10, ddio, ddr input, quartuspro
    • Replies: 0
    • Views: 198
    May 14th, 2018, 04:21 AM Go to last post
  17. Driving Ladder DAC

    Started by Camper, May 8th, 2018 04:14 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 882
    May 13th, 2018, 06:25 AM Go to last post
  18. Erased CFM0 on Max 10 - Can't find JTAG Connection

    Started by smiles, May 10th, 2018 02:53 AM
    cfm, erase, flash, max10, ufm
    • Replies: 2
    • Views: 305
    May 10th, 2018, 09:42 PM Go to last post
    • Replies: 1
    • Views: 300
    May 8th, 2018, 06:42 AM Go to last post
    • Replies: 4
    • Views: 448
    May 8th, 2018, 01:00 AM Go to last post
  19. MEN F210, Cyclone II and Linux

    Started by cifvts, May 4th, 2018 01:38 AM
    • Replies: 0
    • Views: 289
    May 4th, 2018, 01:38 AM Go to last post
  20. DE1 SoC board USB port

    Started by fatimaharr, May 2nd, 2018 01:03 AM
    de1soc, usb
    • Replies: 1
    • Views: 359
    May 3rd, 2018, 07:24 PM Go to last post
  21. Transceiver Rate Match FIFO - Why is it needed?

    Started by DRC, October 16th, 2012 02:53 PM
    • Replies: 6
    • Views: 36,727
    May 3rd, 2018, 11:50 AM Go to last post
  22. Question Stratix II cannot config with JTAG or AS

    Started by qdavid64, May 1st, 2018 05:30 AM
    config_done, ep2s60, stratix ii
    • Replies: 3
    • Views: 411
    May 3rd, 2018, 07:30 AM Go to last post
  23. switching VCCIO Max5 during operation CPLD

    Started by keln, April 27th, 2018 07:44 AM
    • Replies: 1
    • Views: 372
    May 2nd, 2018, 07:42 PM Go to last post
  24. Timequest constraints for a dynamically phase-shifted PLL

    Started by eh291, April 13th, 2018 03:20 PM
    4 Pages
    1 2 3 ... 4
    • Replies: 30
    • Views: 1,986
    May 2nd, 2018, 10:14 AM Go to last post

Thread Display Options

Use this control to limit the display of threads to those newer than the specified time frame.

Allows you to choose the data by which the thread list will be sorted.

Order threads in...

Note: when sorting by date, 'descending order' will show the newest results first.

Icon Legend

Contains unread posts
Contains unread posts
Contains no unread posts
Contains no unread posts
More than 15 replies or 150 views
Hot thread with unread posts
More than 15 replies or 150 views
Hot thread with no unread posts
Closed Thread
Thread is closed
Thread Contains a Message Written By You
You have posted in this thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •