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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 3
    • Views: 73
    Today, 07:58 PM Go to last post
  1. Error (15684)

    Started by fabf, September 20th, 2016 12:14 PM
    • Replies: 2
    • Views: 348
    Today, 12:45 PM Go to last post
  2. SDC for ALTCLKCTRL

    Started by shaiko, January 15th, 2017 11:55 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 210
    Today, 12:35 PM Go to last post
  3. DE0-Nano: Want to learn how to use

    Started by tdg8934, Yesterday 11:26 AM
    • Replies: 3
    • Views: 88
    Today, 11:33 AM Go to last post
  4. Read program from the CPLD Altera MAX7128S

    Started by plml73, Yesterday 10:42 PM
    • Replies: 1
    • Views: 50
    Today, 11:02 AM Go to last post
  5. cyclone iii problem with ddr sdram pin

    Started by pangsong, March 26th, 2009 11:34 PM
    • Replies: 7
    • Views: 49,403
    January 15th, 2017, 10:48 PM Go to last post
  6. Max10 PCB Layout - Unused Pins

    Started by newtham, April 5th, 2016 01:36 PM
    2 Pages
    1 2
    layout, max10, pcb
    • Replies: 13
    • Views: 1,436
    January 15th, 2017, 05:23 PM Go to last post
  7. NEED HELP FOR DE0's UART

    Started by bomobye, December 17th, 2016 06:49 AM
    • Replies: 2
    • Views: 209
    January 13th, 2017, 07:24 AM Go to last post
  8. MAX10: JTAG sharing not working -- how to erase fw-image?

    Started by luigi70, January 12th, 2017 10:57 AM
    erase firmware, jtag sharing, jtagen, max10, nconfig
    • Replies: 1
    • Views: 78
    January 13th, 2017, 04:30 AM Go to last post
  9. ALTPLL vs ALTPLL_RECONFIG

    Started by dmitryl_amarel, January 5th, 2017 12:35 AM
    • Replies: 5
    • Views: 189
    January 13th, 2017, 03:08 AM Go to last post
  10. new to NIOS II. Need help for my requirement.

    Started by thunderbolt, January 6th, 2017 05:53 PM
    • Replies: 2
    • Views: 147
    January 9th, 2017, 10:47 PM Go to last post
  11. ALTCLKCTRL vs PLL with 2 reference clocks

    Started by shaiko, January 8th, 2017 11:34 PM
    • Replies: 3
    • Views: 108
    January 9th, 2017, 04:53 AM Go to last post
  12. max10 dual image + dual hex for nios

    Started by Andy Right, July 24th, 2015 09:58 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 2,239
    January 6th, 2017, 03:36 PM Go to last post
  13. EPF10k10 configuration time?

    Started by Mux, September 30th, 2012 08:28 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 35,339
    January 6th, 2017, 03:14 PM Go to last post
  14. Gated Clock + Clock MUX-> what primitives to use?

    Started by dmitryl_amarel, January 5th, 2017 05:51 AM
    • Replies: 2
    • Views: 139
    January 6th, 2017, 11:55 AM Go to last post
  15. Adding + reconfig of ALTPLL to the Project

    Started by dmitryl_amarel, January 5th, 2017 04:51 AM
    • Replies: 1
    • Views: 92
    January 6th, 2017, 02:37 AM Go to last post
  16. Altera DE2-115 (Cyclone IV) VS. Altera Cyclone V SoC

    Started by eLg, January 4th, 2017 05:38 PM
    fpga soc
    • Replies: 2
    • Views: 149
    January 5th, 2017, 06:30 PM Go to last post
  17. Question Fractional pll reconfig on cyclone v - share with mux

    Started by foft, January 5th, 2017 01:22 PM
    cyclonev, fpll, pll, reconfig
    • Replies: 0
    • Views: 68
    January 5th, 2017, 01:22 PM Go to last post
  18. JTAG pin sharing problem

    Started by qdkdcq, March 31st, 2016 02:49 AM
    max10 jtag sharing pin
    • Replies: 1
    • Views: 489
    January 5th, 2017, 10:22 AM Go to last post
  19. Cyclone 5 maximum size DDR3

    Started by sherif123, January 1st, 2017 05:23 AM
    • Replies: 3
    • Views: 176
    January 5th, 2017, 03:15 AM Go to last post
    • Replies: 2
    • Views: 182
    January 5th, 2017, 01:13 AM Go to last post
  20. moving average filter - unkown signal issue

    Started by RobertLyle, January 4th, 2017 05:05 AM
    • Replies: 5
    • Views: 187
    January 5th, 2017, 12:20 AM Go to last post
  21. Unhappy Scrolling Text - 7 Segment Display on DE0-CV

    Started by Komotonoto, January 3rd, 2017 05:05 PM
    • Replies: 2
    • Views: 130
    January 4th, 2017, 08:02 AM Go to last post
  22. MAX10 ADC doesn't start during power on

    Started by kattice, April 5th, 2016 11:18 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 1,740
    January 3rd, 2017, 02:05 PM Go to last post
  23. Error when using University Program VwF

    Started by powermax, December 30th, 2016 11:58 AM
    • Replies: 2
    • Views: 264
    January 3rd, 2017, 09:41 AM Go to last post
  24. Configuration Walkthrough

    Started by vinhael, January 2nd, 2017 04:32 PM
    configuration
    • Replies: 0
    • Views: 75
    January 2nd, 2017, 04:32 PM Go to last post
  25. MAX10 User-Specified ADC Logic Simulation Output

    Started by rene.holtslag, December 21st, 2016 04:57 AM
    adc, max10, modular, simulation
    • Replies: 3
    • Views: 210
    January 2nd, 2017, 08:02 AM Go to last post
  26. Cyclone 5 custom board PLL issues

    Started by sherif123, December 25th, 2016 03:21 AM
    • Replies: 9
    • Views: 319
    January 2nd, 2017, 02:45 AM Go to last post
  27. Is it OK to use clock in the logic decisions?

    Started by radivoje, December 30th, 2016 08:42 AM
    • Replies: 3
    • Views: 163
    December 30th, 2016, 11:49 PM Go to last post
  28. is it a good choice to use max10 in my new project?

    Started by qd0090, December 14th, 2016 06:45 PM
    • Replies: 4
    • Views: 281
    December 29th, 2016, 05:35 AM Go to last post

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