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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Max10 10M08SAU169 Layout, PDN tool required?

    Started by synchronous, July 23rd, 2017 04:16 AM
    de-coupling caps, max10, pcb layout, pdn
    • Replies: 7
    • Views: 282
    Yesterday, 10:46 AM Go to last post
    • Replies: 4
    • Views: 520
    Yesterday, 01:51 AM Go to last post
  2. Arria V GZ POR trip levels

    Started by Brian Thompson, July 25th, 2017 08:32 PM
    • Replies: 0
    • Views: 60
    July 25th, 2017, 08:32 PM Go to last post
  3. Question clock problem on De0 nano board (schematics file)

    Started by Irian, July 25th, 2017 04:49 PM
    • Replies: 0
    • Views: 64
    July 25th, 2017, 04:49 PM Go to last post
  4. DDS designed by FPGA

    Started by seongjinkim, July 24th, 2017 11:39 PM
    • Replies: 1
    • Views: 104
    July 25th, 2017, 12:55 PM Go to last post
  5. Question MAX10 pin too close to PLL clock

    Started by DoctornoUA, May 11th, 2016 09:52 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 2,172
    July 25th, 2017, 10:45 AM Go to last post
  6. Data Transfer from PC to FPGA

    Started by jaribro, July 23rd, 2017 10:48 PM
    • Replies: 4
    • Views: 191
    July 25th, 2017, 07:25 AM Go to last post
  7. Pin location is too close to PLL clock input pin

    Started by RiccardoRuf, July 25th, 2017 05:03 AM
    • Replies: 0
    • Views: 62
    July 25th, 2017, 05:03 AM Go to last post
  8. Booting time of MAX 10 FPGA

    Started by hareesh9415, July 24th, 2017 11:15 PM
    fpga, max 10, power sequencing
    • Replies: 2
    • Views: 97
    July 25th, 2017, 12:55 AM Go to last post
  9. Cyclone V GX using all 6 transceivers in both directions

    Started by tkhansen@bksv.com, October 8th, 2015 06:10 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 3,590
    July 24th, 2017, 06:16 AM Go to last post
  10. About problem with using EMAC splitter and GMII_TO_RGMII

    Started by hwada, July 23rd, 2017 08:12 PM
    • Replies: 0
    • Views: 75
    July 23rd, 2017, 08:12 PM Go to last post
  11. Low cost FPGAs with dual Gigabit Ethernet controller.

    Started by fiedel, July 21st, 2017 07:19 AM
    • Replies: 1
    • Views: 213
    July 21st, 2017, 10:29 AM Go to last post
  12. Multiple Configuration File for Cyclone IV E

    Started by shauk, May 30th, 2017 04:51 AM
    cyclone iv e
    • Replies: 6
    • Views: 809
    July 21st, 2017, 01:06 AM Go to last post
  13. Two kinds of EP4SE530H35I3N

    Started by eRen, July 20th, 2017 08:15 AM
    • Replies: 1
    • Views: 151
    July 20th, 2017, 08:39 AM Go to last post
  14. Max10 10m25 dual supply; jtag volatge

    Started by nicx82, July 19th, 2017 08:21 AM
    • Replies: 1
    • Views: 166
    July 20th, 2017, 01:55 AM Go to last post
  15. PLL is not working in Cylcone V GX (Using Integer PLL)

    Started by kharthik, July 19th, 2017 04:19 AM
    • Replies: 4
    • Views: 206
    July 20th, 2017, 01:38 AM Go to last post
  16. MAX V CFM write/erase fatigue failure mode

    Started by sonictj, July 19th, 2017 11:49 PM
    • Replies: 0
    • Views: 98
    July 19th, 2017, 11:49 PM Go to last post
  17. how to set values in the same register in the PL side

    Started by Sfato, July 19th, 2017 03:56 AM
    • Replies: 0
    • Views: 127
    July 19th, 2017, 03:56 AM Go to last post
  18. banks sharing VCCPD pins

    Started by rod@ariradesign.com, July 18th, 2017 03:14 PM
    • Replies: 1
    • Views: 155
    July 19th, 2017, 03:05 AM Go to last post
  19. Post UFM verification method (VCS)

    Started by Tadanori_ikeda, July 13th, 2017 09:19 PM
    usm synopsys vcs
    • Replies: 1
    • Views: 255
    July 18th, 2017, 05:01 PM Go to last post
  20. How to disable I/O Bank Source Voltage

    Started by serway, July 18th, 2017 06:57 AM
    • Replies: 2
    • Views: 202
    July 18th, 2017, 11:48 AM Go to last post
  21. SignalTap fails timing often

    Started by rozsatib, July 18th, 2017 06:24 AM
    • Replies: 6
    • Views: 298
    July 18th, 2017, 11:25 AM Go to last post
  22. Design altera FPGA board

    Started by creatives, July 16th, 2017 06:48 AM
    board design, fpga
    • Replies: 4
    • Views: 302
    July 18th, 2017, 06:38 AM Go to last post
  23. MAX10: Altera GPIO Lite

    Started by vlrean, July 18th, 2017 02:57 AM
    • Replies: 0
    • Views: 154
    July 18th, 2017, 02:57 AM Go to last post
    • Replies: 0
    • Views: 171
    July 17th, 2017, 05:54 AM Go to last post
  24. .jic file checksum

    Started by denoise, July 17th, 2017 05:06 AM
    checksum, crc, jic
    • Replies: 0
    • Views: 137
    July 17th, 2017, 05:06 AM Go to last post
  25. MAX10 Remote system Upgrade

    Started by sruthi.1914, July 17th, 2017 03:31 AM
    cpld, max 10 - rsu, max 10- reconfiguration
    • Replies: 0
    • Views: 127
    July 17th, 2017, 03:31 AM Go to last post
  26. MAX10 Dual Configuraion IP

    Started by sruthi.1914, July 17th, 2017 03:13 AM
    cpld, max10 - rsu, remote system upgrade
    • Replies: 0
    • Views: 119
    July 17th, 2017, 03:13 AM Go to last post
  27. There are no Nios II CPUs

    Started by bassem, May 23rd, 2012 08:10 AM
    • Replies: 3
    • Views: 34,562
    July 16th, 2017, 10:39 PM Go to last post
  28. STRATIX10 Configuration time

    Started by GVAISMAN, July 3rd, 2017 11:05 PM
    • Replies: 1
    • Views: 282
    July 16th, 2017, 10:37 PM Go to last post

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