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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. HMC pins in the CycloneV

    Started by serg1976, Today 10:06 AM
    • Replies: 1
    • Views: 75
    Today, 06:25 PM Go to last post
  2. Post sdo file not generated in altera

    Started by shyamk, Today 02:46 AM
    • Replies: 1
    • Views: 71
    Today, 04:37 PM Go to last post
  3. Maximum inputs per LAB

    Started by eugenek, Today 03:18 AM
    • Replies: 8
    • Views: 119
    Today, 03:55 PM Go to last post
  4. Data Transfer from FPGA-to-HPS

    Started by andrew44, June 12th, 2018 11:54 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 642
    Today, 02:05 PM Go to last post
  5. How to design ALM for Aria 10?

    Started by g_tushar, June 18th, 2018 04:26 PM
    alm, multiplexer, verilog
    • Replies: 1
    • Views: 171
    Today, 11:51 AM Go to last post
  6. PFL can not program my FLASH

    Started by xinbingma, May 17th, 2014 08:57 PM
    pfl
    • Replies: 1
    • Views: 14,373
    Today, 11:18 AM Go to last post
  7. About path delay in my FPGA

    Started by pan307398668, June 18th, 2018 07:38 PM
    path delay
    • Replies: 2
    • Views: 168
    Today, 03:39 AM Go to last post
  8. nStatus held low Cyclone IV EP4CE6E22

    Started by Labo_elec, June 18th, 2018 12:24 AM
    • Replies: 3
    • Views: 204
    Today, 03:19 AM Go to last post
  9. cyglone 5 gt interface for ads5263

    Started by thieulam, June 15th, 2016 02:28 AM
    • Replies: 4
    • Views: 1,304
    Today, 12:53 AM Go to last post
  10. Spectrum analyzer

    Started by espanyola, June 16th, 2018 05:42 AM
    • Replies: 1
    • Views: 194
    Yesterday, 05:55 PM Go to last post
    • Replies: 0
    • Views: 81
    Yesterday, 05:21 PM Go to last post
    • Replies: 0
    • Views: 105
    Yesterday, 10:30 AM Go to last post
    • Replies: 7
    • Views: 348
    Yesterday, 06:05 AM Go to last post
  11. Interface SD Card through GPIO on DE0-Nano

    Started by macoskey, June 15th, 2018 12:24 PM
    cyclone iv, de0-nano, raspberry pi, sd card
    • Replies: 3
    • Views: 232
    Yesterday, 05:01 AM Go to last post
    • Replies: 1
    • Views: 161
    Yesterday, 04:01 AM Go to last post
  12. EPCS4SI8N bonding diagram

    Started by smithhk, Yesterday 01:19 AM
    • Replies: 0
    • Views: 116
    Yesterday, 01:19 AM Go to last post
  13. Problem with Max 10 I've never seen before

    Started by ddavidd, June 18th, 2018 03:37 PM
    • Replies: 1
    • Views: 148
    June 18th, 2018, 05:22 PM Go to last post
  14. Cyclone IV EP4CE10E22 circuit examples

    Started by clros, June 17th, 2018 04:55 AM
    • Replies: 1
    • Views: 182
    June 18th, 2018, 09:13 AM Go to last post
  15. max10 - external reset

    Started by Mux, June 17th, 2018 09:39 PM
    max10 reset
    • Replies: 0
    • Views: 132
    June 17th, 2018, 09:39 PM Go to last post
  16. Implementing a Large RAM on Cyclone II - is it possible?

    Started by dan11, June 16th, 2018 01:07 PM
    cyclone ii; ram
    • Replies: 4
    • Views: 220
    June 17th, 2018, 02:03 PM Go to last post
  17. Cyclone IV FPGA (EP4CE10E22) circuit

    Started by clros, June 17th, 2018 05:17 AM
    • Replies: 0
    • Views: 187
    June 17th, 2018, 05:17 AM Go to last post
  18. Max10 Jtag pins as Differential I/O.

    Started by Kozha, June 10th, 2018 12:36 AM
    • Replies: 4
    • Views: 379
    June 17th, 2018, 04:46 AM Go to last post
  19. 5AGXFB3H4F35C5NES device support

    Started by PonyoWoo, June 15th, 2018 08:53 AM
    arria v, arria v gx, arria v gx starter kit, device support
    • Replies: 1
    • Views: 182
    June 16th, 2018, 06:09 PM Go to last post
    • Replies: 1
    • Views: 207
    June 15th, 2018, 06:44 AM Go to last post
  20. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 3
    • Views: 1,662
    June 14th, 2018, 07:14 AM Go to last post
  21. MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

    Started by Vadim_GMI, June 14th, 2018 12:41 AM
    i/o, max10, pll, voltage level
    • Replies: 2
    • Views: 198
    June 14th, 2018, 03:27 AM Go to last post
  22. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    • Replies: 9
    • Views: 389
    June 13th, 2018, 10:30 PM Go to last post
  23. Can I configure Cyclone V GT from Parallel Flash?

    Started by shy@navatek.com, June 13th, 2018 08:46 PM
    • Replies: 0
    • Views: 155
    June 13th, 2018, 08:46 PM Go to last post
  24. Timing failure on internal paths

    Started by mohsinele83, June 8th, 2018 03:12 AM
    • Replies: 4
    • Views: 355
    June 13th, 2018, 03:01 AM Go to last post
  25. Strange PLL Clock causing me failing paths in cyc V design

    Started by Hendrik2k1, June 4th, 2018 04:32 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 796
    June 13th, 2018, 02:46 AM Go to last post

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