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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Arria 10 Native Transceiver PHY - 10GBASE-R

    Started by xnovak1m, August 16th, 2017 07:12 AM
    10gbase-r, arria 10, transceiver, xcvr
    • Replies: 1
    • Views: 169
    Today, 07:41 AM Go to last post
  2. MAX 10 in place of Cyclone IV

    Started by Lurkers, August 8th, 2017 07:44 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 665
    Today, 01:28 AM Go to last post
  3. Cyclone V ALTLVDS_RX clocking

    Started by karlovic, August 8th, 2017 01:10 AM
    altlvds, cyclone v, fpll, lvds, pll
    • Replies: 1
    • Views: 239
    Yesterday, 11:34 PM Go to last post
  4. Post Triple Speed Ethernet

    Started by victor298, August 18th, 2017 12:33 AM
    • Replies: 4
    • Views: 193
    Yesterday, 10:23 PM Go to last post
  5. Quartus Error 35030

    Started by sonicsmooth, Yesterday 10:50 AM
    • Replies: 2
    • Views: 105
    Yesterday, 01:02 PM Go to last post
  6. Help needed in understanding "Net Delay Summary"

    Started by poornacs, August 21st, 2017 07:28 PM
    • Replies: 1
    • Views: 119
    Yesterday, 02:44 AM Go to last post
    • Replies: 7
    • Views: 328
    August 21st, 2017, 07:36 PM Go to last post
  7. FPGA to SFP

    Started by kharthik, August 10th, 2017 11:04 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 645
    August 21st, 2017, 08:35 AM Go to last post
    • Replies: 2
    • Views: 202
    August 20th, 2017, 11:57 PM Go to last post
  8. JTAG chain

    Started by Lurkers, August 18th, 2017 03:27 PM
    • Replies: 6
    • Views: 258
    August 20th, 2017, 05:56 PM Go to last post
  9. Pin matching issue on my Cyclone V GX Starter Kit

    Started by virgilio72, August 19th, 2017 02:31 AM
    • Replies: 3
    • Views: 202
    August 19th, 2017, 01:52 PM Go to last post
  10. Global, Local, Regional, and Peripheral clocks

    Started by dmitryl, November 30th, 2015 02:23 AM
    2 Pages
    1 2
    • Replies: 16
    • Views: 2,903
    August 18th, 2017, 04:10 PM Go to last post
  11. Mega Wizard dual Clock FIFO Strange behavior !!!!!

    Started by Muhammad, August 18th, 2017 03:25 AM
    • Replies: 9
    • Views: 279
    August 18th, 2017, 09:53 AM Go to last post
    • Replies: 1
    • Views: 796
    August 18th, 2017, 02:08 AM Go to last post
  12. Cyclone IV E Configuration with Enhanced Configuration Devices

    Started by shauk, August 16th, 2017 04:23 AM
    • Replies: 3
    • Views: 212
    August 16th, 2017, 06:16 AM Go to last post
  13. Question Timing parameters of USB Blaster 1

    Started by droe, August 14th, 2017 01:36 AM
    arria10, jtag, timing, usb blaster
    • Replies: 6
    • Views: 347
    August 16th, 2017, 03:05 AM Go to last post
  14. Connecting a PCIe board to a PC

    Started by shaiko, August 16th, 2017 01:37 AM
    • Replies: 1
    • Views: 167
    August 16th, 2017, 02:52 AM Go to last post
  15. Question Looking for FPGA freelancer

    Started by testex, August 14th, 2017 04:57 AM
    contactor, contract, freelance, freelancer
    • Replies: 2
    • Views: 282
    August 15th, 2017, 11:46 PM Go to last post
  16. MAX 10 fails to run JTAG loaded SOF

    Started by jshamlet, August 1st, 2017 06:52 AM
    • Replies: 3
    • Views: 393
    August 15th, 2017, 03:53 AM Go to last post
  17. IO-TRISTATE Buffer issue with MAX10

    Started by fpgaengineerfrankfurt, August 15th, 2017 03:46 AM
    io buffer, max10, tristate
    • Replies: 0
    • Views: 142
    August 15th, 2017, 03:46 AM Go to last post
  18. Cyclone V input slew rate

    Started by rozsatib, August 13th, 2017 10:16 AM
    • Replies: 0
    • Views: 173
    August 13th, 2017, 10:16 AM Go to last post
  19. Flex 10k LPM_ADD_SUB issue

    Started by Mux, August 12th, 2017 08:07 PM
    9.2, epf10k10, lpm_add_sub
    • Replies: 1
    • Views: 191
    August 12th, 2017, 10:14 PM Go to last post
  20. 48Mhz XTAL or 12MHz thru PLL x4?

    Started by Lurkers, August 11th, 2017 02:29 PM
    • Replies: 4
    • Views: 353
    August 12th, 2017, 07:47 PM Go to last post
  21. JTAG Boundary Scan Register order for unpackaged device

    Started by ejstrates, August 10th, 2017 10:45 AM
    • Replies: 1
    • Views: 248
    August 11th, 2017, 06:15 AM Go to last post
  22. Question Remote System Update with Max 10 10M16

    Started by KonradH, January 19th, 2017 11:26 PM
    dualconfiguration, max10, qsys, rsu
    • Replies: 8
    • Views: 1,405
    August 11th, 2017, 04:50 AM Go to last post
  23. about MAX V ALTUFM Parallel Interface Timing Spec

    Started by olkhram, August 10th, 2017 02:16 AM
    • Replies: 0
    • Views: 196
    August 10th, 2017, 02:16 AM Go to last post
  24. MAX10 10M50SA power supply requirement for analog feature

    Started by sieg70, August 8th, 2017 02:28 AM
    • Replies: 1
    • Views: 281
    August 9th, 2017, 06:58 AM Go to last post
  25. 10M08SAE144 PCB package drawing question

    Started by technobob, August 8th, 2017 10:11 AM
    • Replies: 1
    • Views: 285
    August 9th, 2017, 06:11 AM Go to last post
  26. Designing a SPI slave

    Started by Lurkers, July 31st, 2017 04:31 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 1,036
    August 7th, 2017, 04:37 AM Go to last post
  27. does MAX10 10M50SA support CFM UFM and RSU?

    Started by sieg70, July 31st, 2017 02:41 AM
    • Replies: 2
    • Views: 354
    August 7th, 2017, 02:53 AM Go to last post

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