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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. DE2-70 SRAM timing question

    Started by brentnallt, April 27th, 2017 07:04 AM
    de2-70, memory, sram, ssram
    • Replies: 2
    • Views: 95
    Today, 11:15 AM Go to last post
  2. Cyclone V HPS UART, can't rx data

    Started by cdhewitt88, November 4th, 2015 09:09 AM
    • Replies: 6
    • Views: 1,758
    Today, 05:06 AM Go to last post
  3. 5CEBA9 Drop-in compatibility

    Started by buran16, Yesterday 01:55 AM
    • Replies: 1
    • Views: 70
    Yesterday, 06:50 AM Go to last post
  4. DDR3 burst lenght

    Started by CV_HAAN, Yesterday 01:24 AM
    burst, ddr3
    • Replies: 0
    • Views: 44
    Yesterday, 01:24 AM Go to last post
  5. Question MAX10 Programmable IOE Delay

    Started by masavoyat, Yesterday 01:21 AM
    max10, programmable ioe delay
    • Replies: 0
    • Views: 43
    Yesterday, 01:21 AM Go to last post
  6. MAX 10 internal configuration

    Started by KVL, April 27th, 2017 10:06 PM
    • Replies: 5
    • Views: 110
    Yesterday, 12:47 AM Go to last post
  7. Programming tools on ARRIA 10 with windows XP

    Started by julien.gicquiaux, April 27th, 2017 07:42 AM
    arria 10 xp
    • Replies: 4
    • Views: 130
    April 27th, 2017, 11:33 PM Go to last post
  8. Routing USB through FPGA

    Started by Camper, April 26th, 2017 02:40 AM
    • Replies: 7
    • Views: 306
    April 27th, 2017, 01:51 PM Go to last post
  9. How could I use the 'ENA' pin of the embedded multiplier?

    Started by tyskin, April 27th, 2017 10:23 AM
    • Replies: 1
    • Views: 100
    April 27th, 2017, 12:20 PM Go to last post
  10. JTAG Programming successfull but no effect at the ouput

    Started by mohsin_qau, April 20th, 2017 11:11 PM
    • Replies: 6
    • Views: 372
    April 27th, 2017, 02:21 AM Go to last post
    • Replies: 2
    • Views: 179
    April 26th, 2017, 10:46 PM Go to last post
  11. set_input_delay And set_output_delay .SDC Constraints

    Started by techno-rogue, March 29th, 2017 07:33 AM
    3 Pages
    1 2 3
    • Replies: 24
    • Views: 1,531
    April 26th, 2017, 02:41 AM Go to last post
  12. How to check throughput?

    Started by aria_strat, April 25th, 2017 10:59 AM
    arria 10, latency, optimization, performance, throughput
    • Replies: 0
    • Views: 106
    April 25th, 2017, 10:59 AM Go to last post
    • Replies: 2
    • Views: 265
    April 25th, 2017, 03:20 AM Go to last post
  13. implementing distance sensor in my code

    Started by Skvaknin@gmail.com, April 19th, 2017 10:43 PM
    • Replies: 8
    • Views: 424
    April 25th, 2017, 01:55 AM Go to last post
  14. Booting NIOS from QSPI

    Started by ela05jdc, April 12th, 2017 08:35 AM
    boot, eds, nios, pfl, qspi
    • Replies: 3
    • Views: 367
    April 25th, 2017, 01:27 AM Go to last post
  15. Cyclone V GT Native PHY for 5Gbps USB 3.0?

    Started by JohnG300C, April 24th, 2017 07:06 PM
    • Replies: 0
    • Views: 128
    April 24th, 2017, 07:06 PM Go to last post
  16. mutliple VHDL designs maneuvering

    Started by Skvaknin@gmail.com, April 22nd, 2017 03:37 AM
    • Replies: 1
    • Views: 226
    April 22nd, 2017, 07:31 AM Go to last post
  17. MAX10 flash memory address mapping

    Started by sruthi.1914, April 19th, 2017 11:58 PM
    altera on chip flash, cpld, max10
    • Replies: 1
    • Views: 266
    April 21st, 2017, 01:21 PM Go to last post
  18. DE0-NANO Board SDC file and PLL

    Started by shauk, April 21st, 2017 02:14 AM
    • Replies: 1
    • Views: 201
    April 21st, 2017, 02:53 AM Go to last post
    • Replies: 5
    • Views: 2,324
    April 20th, 2017, 06:35 PM Go to last post
    • Replies: 2
    • Views: 241
    April 20th, 2017, 05:06 AM Go to last post
  19. MAX10 Discrete I2C implementation of RSU issue

    Started by OG_973, April 20th, 2017 03:37 AM
    • Replies: 1
    • Views: 176
    April 20th, 2017, 03:53 AM Go to last post
  20. Question PLDT-2 Trainer--

    Started by Ray Leiter, April 16th, 2017 04:25 PM
    pldt-2, rayl
    • Replies: 1
    • Views: 196
    April 19th, 2017, 01:25 AM Go to last post
  21. Why only Soft PCS for Altera's XAUI IP in Arria 10 GX?

    Started by fpgabuilder, April 18th, 2017 01:18 PM
    arria 10 gx, soft pcs, xaui
    • Replies: 0
    • Views: 173
    April 18th, 2017, 01:18 PM Go to last post
  22. Issue Configuring MAX10: "Can't Access JTAG Chain"

    Started by jrx07, April 11th, 2017 08:08 PM
    • Replies: 1
    • Views: 311
    April 17th, 2017, 10:07 AM Go to last post
  23. DDR3 HMC Timing issue with Qsys(device:5CGXFC5C6F27C7)

    Started by kerb, February 4th, 2015 10:18 PM
    • Replies: 2
    • Views: 4,206
    April 16th, 2017, 07:40 AM Go to last post
  24. error of PCIE PERST_N whe running fitter!

    Started by gransport, April 9th, 2017 11:51 PM
    • Replies: 3
    • Views: 329
    April 16th, 2017, 06:49 AM Go to last post
  25. DE0-Nano: Want to learn how to use

    Started by tdg8934, January 17th, 2017 10:26 AM
    • Replies: 4
    • Views: 461
    April 15th, 2017, 01:25 PM Go to last post
  26. Question MAX10 Flash Memory specifications

    Started by seairth, February 8th, 2015 05:24 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 5,415
    April 14th, 2017, 04:30 PM Go to last post

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