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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 7
    • Views: 304
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  1. Gated Clock + Clock MUX-> what primitives to use?

    Started by dmitryl_amarel, January 5th, 2017 04:51 AM
    • Replies: 3
    • Views: 499
    June 24th, 2017, 08:27 AM Go to last post
    • Replies: 1
    • Views: 10,555
    June 23rd, 2017, 09:41 AM Go to last post
    • Replies: 0
    • Views: 28
    June 23rd, 2017, 04:44 AM Go to last post
  2. Development Software Tool for old ADHL *.tdf code

    Started by Lynard, June 21st, 2017 12:13 PM
    • Replies: 2
    • Views: 193
    June 23rd, 2017, 02:40 AM Go to last post
    • Replies: 0
    • Views: 137
    June 22nd, 2017, 09:49 PM Go to last post
  3. Question How to Interface 10M04SCU169 with Host processor

    Started by santosh_bongane, June 13th, 2017 05:16 PM
    2 Pages
    1 2
    • Replies: 16
    • Views: 1,818
    June 22nd, 2017, 06:40 PM Go to last post
  4. Unhappy Programming Cyclone EP1C4F324I7N

    Started by Euticus, June 22nd, 2017 07:28 AM
    cyclone, program, vhdl
    • Replies: 1
    • Views: 147
    June 22nd, 2017, 07:40 AM Go to last post
  5. MAX10 no response after power cycle

    Started by andywiis, June 13th, 2017 04:05 AM
    • Replies: 3
    • Views: 299
    June 22nd, 2017, 12:55 AM Go to last post
  6. Timing for MAX 10 ADC Control Core Only interace logic

    Started by Dale Puls, June 15th, 2017 01:06 PM
    adc, condtol core only
    • Replies: 1
    • Views: 230
    June 21st, 2017, 06:44 AM Go to last post
  7. CVP on Arria 10

    Started by vernmid, May 26th, 2017 01:39 AM
    0xffffffff, arria 10, cvp, pcie
    • Replies: 1
    • Views: 360
    June 21st, 2017, 04:32 AM Go to last post
  8. MAX10: JTAG sharing not working -- how to erase fw-image?

    Started by luigi70, January 12th, 2017 09:57 AM
    erase firmware, jtag sharing, jtagen, max10, nconfig
    • Replies: 2
    • Views: 660
    June 21st, 2017, 03:28 AM Go to last post
  9. Can't fit design in Cyclone V GX

    Started by sham, June 1st, 2017 11:05 AM
    cyclone v, my first fpga, quartus prime lite
    • Replies: 5
    • Views: 666
    June 20th, 2017, 10:40 PM Go to last post
    • Replies: 12
    • Views: 903
    June 20th, 2017, 06:51 PM Go to last post
  10. Arria 10 GX pcie and xaui transceiver interaction

    Started by fpgabuilder, June 19th, 2017 03:58 PM
    arria 10, pcie, transceivers, xaui
    • Replies: 3
    • Views: 222
    June 20th, 2017, 09:04 AM Go to last post
  11. Unable to simulate MAX 10 ADC

    Started by RobS, June 15th, 2017 04:03 AM
    adc
    • Replies: 1
    • Views: 214
    June 19th, 2017, 11:58 PM Go to last post
  12. Looking for specific Stratix product

    Started by qh9433q, June 15th, 2017 11:23 AM
    altera, product, stratix
    • Replies: 4
    • Views: 424
    June 18th, 2017, 10:48 PM Go to last post
  13. real time recognition engine

    Started by nhoxheokutee, June 18th, 2017 01:32 AM
    • Replies: 0
    • Views: 162
    June 18th, 2017, 01:32 AM Go to last post
  14. Clock Data Recovery in Stratix V Transceiver

    Started by new_user, June 11th, 2017 07:38 AM
    • Replies: 1
    • Views: 297
    June 15th, 2017, 07:21 PM Go to last post
  15. Cyclone V Clock Not Toggling

    Started by johnab, June 15th, 2017 05:44 AM
    • Replies: 4
    • Views: 379
    June 15th, 2017, 09:19 AM Go to last post
    • Replies: 0
    • Views: 196
    June 15th, 2017, 07:11 AM Go to last post
  16. DE0 Cyclone V GPIO 1-Z switching, RN series

    Started by pavel6490, June 14th, 2017 02:07 PM
    • Replies: 1
    • Views: 230
    June 15th, 2017, 02:26 AM Go to last post
  17. MAX10 10M02SCE144C8G high current draw

    Started by cmorley, June 8th, 2017 02:07 AM
    • Replies: 3
    • Views: 369
    June 14th, 2017, 03:09 AM Go to last post
  18. MAX10 TSD problem (CH 17 ADC)

    Started by usman1818, December 15th, 2015 06:03 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 3,181
    June 13th, 2017, 10:50 AM Go to last post
  19. Instantiate Max 10 ADC in VHDL

    Started by jshamlet, June 12th, 2017 12:41 PM
    max10 adc vhdl
    • Replies: 2
    • Views: 278
    June 13th, 2017, 07:16 AM Go to last post
  20. Arria V DQS

    Started by jerome.blue, December 12th, 2014 06:04 AM
    • Replies: 1
    • Views: 8,067
    June 13th, 2017, 02:28 AM Go to last post
  21. ZDB Mode - How to verify correct routing / resource usage

    Started by derSoe, June 12th, 2017 11:48 PM
    pll, zdb
    • Replies: 0
    • Views: 193
    June 12th, 2017, 11:48 PM Go to last post
  22. Unable to run different versions of altera libraires

    Started by Kalusu, March 20th, 2017 04:56 AM
    • Replies: 2
    • Views: 729
    June 12th, 2017, 10:23 PM Go to last post
    • Replies: 6
    • Views: 584
    June 12th, 2017, 07:48 AM Go to last post
  23. Is there IP catalog in Quartus II 11.0?

    Started by tollinjose, August 6th, 2015 09:09 PM
    ip catalog, pcie, quartus
    • Replies: 5
    • Views: 2,395
    June 11th, 2017, 12:48 PM Go to last post

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