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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

    • Replies: 5
    • Views: 97
    Yesterday, 10:45 PM Go to last post
  1. Unconstrained clock inside J2A Master?

    Started by sstrell, Yesterday 10:01 AM
    • Replies: 1
    • Views: 34
    Yesterday, 09:00 PM Go to last post
  2. Error 10500: VHDL Syntax

    Started by Braindead90, October 31st, 2012 12:40 PM
    3 Pages
    1 2 3
    • Replies: 28
    • Views: 40,361
    Yesterday, 10:29 AM Go to last post
    • Replies: 1
    • Views: 43
    January 21st, 2017, 12:23 PM Go to last post
  3. Angry Quartus 15.1 crashing when going for Tools...License Setup

    Started by fredbk, November 3rd, 2015 01:33 PM
    2 Pages
    1 2
    15.1, crash, quartus
    • Replies: 19
    • Views: 3,220
    January 20th, 2017, 07:39 PM Go to last post
  4. Quartus and Modelsim add libraries automatically

    Started by esteimle, January 20th, 2017 09:04 AM
    • Replies: 1
    • Views: 55
    January 20th, 2017, 09:58 AM Go to last post
  5. Transceiver Toolkit: Meaning of vertical axis? Help :)

    Started by Rivello, January 19th, 2017 02:43 AM
    • Replies: 1
    • Views: 65
    January 20th, 2017, 08:03 AM Go to last post
  6. Unroll VHDL records using Modelsim/TCL

    Started by dev_horst, January 20th, 2017 03:46 AM
    modelsim, tcl
    • Replies: 1
    • Views: 65
    January 20th, 2017, 05:19 AM Go to last post
  7. altera_pll library instantiation error

    Started by esteimle, January 19th, 2017 12:10 PM
    • Replies: 2
    • Views: 65
    January 20th, 2017, 12:40 AM Go to last post
  8. qsys-edit use in a script

    Started by dpoznan, January 19th, 2017 03:16 PM
    command line, qsys
    • Replies: 3
    • Views: 73
    January 19th, 2017, 11:58 PM Go to last post
  9. # Invalid time string specified: in ModelSim

    Started by franchzilla, January 10th, 2012 06:25 PM
    2 Pages
    1 2
    • Replies: 18
    • Views: 36,326
    January 19th, 2017, 08:52 PM Go to last post
  10. Error: Can't launch ModelSim-Altera Simulation software

    Started by silentsnow, November 11th, 2012 03:11 PM
    • Replies: 3
    • Views: 38,535
    January 19th, 2017, 06:14 PM Go to last post
  11. missing sopcinfo file after QSYS system generation?

    Started by JeffreyOHill, January 12th, 2017 05:32 PM
    qsys generate
    • Replies: 1
    • Views: 81
    January 19th, 2017, 11:21 AM Go to last post
  12. Connectivity Checks report folder -> where is it?

    Started by dmitryl_amarel, January 19th, 2017 07:05 AM
    • Replies: 3
    • Views: 91
    January 19th, 2017, 08:10 AM Go to last post
  13. SDRAM Controller will be dropped from Quartus Lite!!

    Started by ep1015, January 19th, 2017 02:21 AM
    • Replies: 3
    • Views: 106
    January 19th, 2017, 04:03 AM Go to last post
    • Replies: 0
    • Views: 43
    January 19th, 2017, 03:20 AM Go to last post
  14. Quartus Prime Standard 16.1 NIOS launch error on Windows 10

    Started by vinayak.rh, January 19th, 2017 02:48 AM
    16.1, nios, prime, quartus, windows
    • Replies: 1
    • Views: 65
    January 19th, 2017, 03:04 AM Go to last post
    • Replies: 0
    • Views: 47
    January 19th, 2017, 01:50 AM Go to last post
  15. Quartus Prime 16.1 - Timing simulation error .sdf file

    Started by RobertLyle, January 19th, 2017 01:04 AM
    • Replies: 0
    • Views: 75
    January 19th, 2017, 01:04 AM Go to last post
  16. FIFORAM ERROR quartus 15.1

    Started by djstar, January 18th, 2017 09:34 AM
    error, fifo, quartus, ram
    • Replies: 0
    • Views: 52
    January 18th, 2017, 09:34 AM Go to last post
  17. QSYS output (synthesis) directory workaround?

    Started by Jo., February 7th, 2014 01:12 AM
    • Replies: 8
    • Views: 20,134
    January 18th, 2017, 06:56 AM Go to last post
    • Replies: 4
    • Views: 128
    January 18th, 2017, 05:45 AM Go to last post
    • Replies: 2
    • Views: 92
    January 18th, 2017, 04:32 AM Go to last post
  18. Cannot the parameters list be empty in SystemVerilog?

    Started by dmitryl_amarel, January 18th, 2017 02:10 AM
    • Replies: 1
    • Views: 71
    January 18th, 2017, 02:50 AM Go to last post
  19. Can't link device to design in System Console

    Started by Rayho, January 18th, 2017 02:25 AM
    • Replies: 0
    • Views: 21
    January 18th, 2017, 02:25 AM Go to last post
  20. Quartus Prime not allowing apparently correct I/O assignment

    Started by Numinus1, September 13th, 2016 02:36 AM
    • Replies: 4
    • Views: 419
    January 18th, 2017, 01:39 AM Go to last post
    • Replies: 3
    • Views: 91
    January 18th, 2017, 01:32 AM Go to last post
  21. Location of logs & reports in Quartus-II

    Started by dmitryl_amarel, January 18th, 2017 12:08 AM
    • Replies: 1
    • Views: 61
    January 18th, 2017, 01:18 AM Go to last post
  22. Synthesis output for multiple driver within one always

    Started by vittal92, January 17th, 2017 02:24 PM
    multiple driver
    • Replies: 4
    • Views: 109
    January 17th, 2017, 11:48 PM Go to last post
  23. Simulation/Testbench files in Quartus-II

    Started by dmitryl_amarel, January 17th, 2017 08:08 AM
    • Replies: 5
    • Views: 127
    January 17th, 2017, 11:44 PM Go to last post

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