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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

    • Replies: 2
    • Views: 76
    Yesterday, 11:23 PM Go to last post
  1. Quartus / Modelsim Compile Order

    Started by moserw, July 21st, 2009 08:51 AM
    • Replies: 4
    • Views: 45,679
    Yesterday, 01:37 AM Go to last post
  2. Timing Corner

    Started by vittal92, December 2nd, 2016 04:03 PM
    • Replies: 0
    • Views: 75
    December 2nd, 2016, 04:03 PM Go to last post
  3. Convert Programming Files tool and multiple Nios processors

    Started by ebber, November 22nd, 2016 04:54 AM
    • Replies: 3
    • Views: 155
    December 1st, 2016, 07:07 AM Go to last post
  4. OpenCL Licensing

    Started by BhavaniT, November 30th, 2016 11:22 PM
    • Replies: 0
    • Views: 79
    November 30th, 2016, 11:22 PM Go to last post
  5. How connect my data to pcie interafce in Qsys?

    Started by Jerry, October 17th, 2013 12:16 AM
    • Replies: 9
    • Views: 25,977
    November 30th, 2016, 08:41 PM Go to last post
  6. Question splitting an output bus on a symbol

    Started by poca, November 30th, 2016 07:50 AM
    • Replies: 3
    • Views: 146
    November 30th, 2016, 08:01 PM Go to last post
    • Replies: 5
    • Views: 140
    November 30th, 2016, 10:34 AM Go to last post
  7. SignalTap II Time Bars not displayed

    Started by corestar, November 29th, 2016 09:04 PM
    • Replies: 0
    • Views: 64
    November 29th, 2016, 09:04 PM Go to last post
  8. Cannot simulate ALTRCLKCTRL

    Started by ymakisme, November 29th, 2016 10:43 AM
    altclkctrl
    • Replies: 0
    • Views: 71
    November 29th, 2016, 10:43 AM Go to last post
  9. net delay timing violations

    Started by psusar, November 28th, 2016 11:08 PM
    • Replies: 1
    • Views: 109
    November 29th, 2016, 07:24 AM Go to last post
    • Replies: 4
    • Views: 189
    November 29th, 2016, 02:38 AM Go to last post
  10. How to utilize programmable delay chain?

    Started by rdb9879, November 26th, 2016 04:46 PM
    • Replies: 9
    • Views: 247
    November 28th, 2016, 01:49 PM Go to last post
  11. Hold time violation

    Started by vhdl_world, November 24th, 2016 07:24 AM
    • Replies: 5
    • Views: 232
    November 28th, 2016, 06:46 AM Go to last post
  12. Modelsim is exiting with code 211.

    Started by ebber, November 17th, 2016 07:09 AM
    • Replies: 6
    • Views: 244
    November 28th, 2016, 05:49 AM Go to last post
  13. Error (14736): Error: Wizard "ALTFP_MULT" cannot be launched.

    Started by qd0090, November 27th, 2016 11:18 PM
    • Replies: 0
    • Views: 92
    November 27th, 2016, 11:18 PM Go to last post
  14. Weird SignalTap behaviour

    Started by justintime, November 24th, 2016 10:15 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 302
    November 26th, 2016, 07:45 AM Go to last post
  15. nativeLink RTL simulation does not start Vsim

    Started by Raph31, November 25th, 2016 05:25 AM
    • Replies: 0
    • Views: 99
    November 25th, 2016, 05:25 AM Go to last post
    • Replies: 2
    • Views: 162
    November 25th, 2016, 04:02 AM Go to last post
    • Replies: 0
    • Views: 112
    November 24th, 2016, 06:10 PM Go to last post
    • Replies: 2
    • Views: 97
    November 23rd, 2016, 11:25 PM Go to last post
  16. download pof file cost too much time

    Started by qd0090, November 23rd, 2016 02:15 AM
    • Replies: 2
    • Views: 116
    November 23rd, 2016, 07:39 PM Go to last post
    • Replies: 3
    • Views: 300
    November 23rd, 2016, 02:04 PM Go to last post
  17. adding megafunctions with uppercase names

    Started by jigal, November 23rd, 2016 05:19 AM
    linux, lowercase, quartus ii, uppercase
    • Replies: 0
    • Views: 94
    November 23rd, 2016, 05:19 AM Go to last post
  18. questions about copy project

    Started by qd0090, November 23rd, 2016 02:07 AM
    • Replies: 0
    • Views: 78
    November 23rd, 2016, 02:07 AM Go to last post
  19. Synchronization Register Chain?

    Started by gnunes7, November 21st, 2016 05:31 PM
    • Replies: 1
    • Views: 112
    November 21st, 2016, 11:32 PM Go to last post
    • Replies: 4
    • Views: 148
    November 21st, 2016, 12:26 PM Go to last post
  20. Why AND gate not working?

    Started by cookie, July 14th, 2015 01:29 AM
    • Replies: 3
    • Views: 887
    November 20th, 2016, 09:11 AM Go to last post
  21. How to merge two or more buses?

    Started by gnunes7, November 18th, 2016 11:42 AM
    • Replies: 3
    • Views: 222
    November 18th, 2016, 11:31 PM Go to last post
  22. Hold violation on source synchronous clocks

    Started by pfrancis, November 16th, 2016 07:08 AM
    • Replies: 5
    • Views: 176
    November 18th, 2016, 04:19 PM Go to last post

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