Page 1 of 284 1231151101 ... LastLast
Threads 1 to 30 of 8510

Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. Fully Synthesizable Fix Point package

    Started by iozana, Today 03:10 AM
    • Replies: 3
    • Views: 55
    Today, 11:30 AM Go to last post
  2. QSYS 17 .0 pro missing .sopcinfo

    Started by BitBuster, Today 05:19 AM
    • Replies: 1
    • Views: 45
    Today, 09:45 AM Go to last post
  3. How to constrain HPS I2C Bus?

    Started by kmorfitt, February 16th, 2017 02:06 AM
    • Replies: 3
    • Views: 484
    Yesterday, 10:50 AM Go to last post
    • Replies: 4
    • Views: 152
    Yesterday, 09:55 AM Go to last post
    • Replies: 1
    • Views: 61
    Yesterday, 09:16 AM Go to last post
  4. quartus on linux

    Started by elf, June 26th, 2017 01:03 AM
    fedora, linux, quartus
    • Replies: 1
    • Views: 98
    Yesterday, 09:04 AM Go to last post
  5. Question Different simulate result from quartus and modelsim

    Started by Jetlin1992, June 26th, 2017 07:16 AM
    • Replies: 4
    • Views: 139
    Yesterday, 06:49 AM Go to last post
  6. TimeQuest Data-Required Time Appears Incorrect

    Started by ErikAnderson11, June 25th, 2017 02:14 PM
    • Replies: 7
    • Views: 270
    June 26th, 2017, 09:09 AM Go to last post
  7. Question Querying design's completion status via Tcl

    Started by mikegray, June 25th, 2017 07:16 PM
    completion, tcl
    • Replies: 0
    • Views: 109
    June 25th, 2017, 07:16 PM Go to last post
  8. Question Glitchs on a counter

    Started by AlexisC, January 15th, 2017 02:18 AM
    • Replies: 2
    • Views: 383
    June 24th, 2017, 01:30 PM Go to last post
    • Replies: 0
    • Views: 135
    June 24th, 2017, 08:39 AM Go to last post
  9. place only option

    Started by aashlesha94, June 23rd, 2017 10:00 AM
    • Replies: 0
    • Views: 145
    June 23rd, 2017, 10:00 AM Go to last post
  10. TimeQuest GUI takes long time when reading .sdc

    Started by vlrean, May 19th, 2017 06:20 AM
    • Replies: 4
    • Views: 597
    June 23rd, 2017, 07:49 AM Go to last post
    • Replies: 1
    • Views: 178
    June 22nd, 2017, 01:15 PM Go to last post
  11. TimeQuest / DE1-SoC Design Contraint File

    Started by martin-91x, June 22nd, 2017 04:11 AM
    • Replies: 2
    • Views: 212
    June 22nd, 2017, 07:27 AM Go to last post
  12. TimeQuest / DE1-SoC Design Contraint File

    Started by martin-91x, June 22nd, 2017 07:24 AM
    • Replies: 1
    • Views: 163
    June 22nd, 2017, 07:26 AM Go to last post
    • Replies: 0
    • Views: 90
    June 21st, 2017, 09:24 AM Go to last post
    • Replies: 3
    • Views: 1,269
    June 21st, 2017, 04:31 AM Go to last post
  13. Vector waveform file and timing simulation resolution

    Started by Activebits, June 21st, 2017 04:31 AM
    • Replies: 0
    • Views: 142
    June 21st, 2017, 04:31 AM Go to last post
  14. matrix array from instantiations

    Started by nizdom, June 21st, 2017 02:00 AM
    • Replies: 1
    • Views: 177
    June 21st, 2017, 03:28 AM Go to last post
  15. Question [Quartus] Organize project files in folders

    Started by avben, June 13th, 2017 07:59 AM
    quartus project
    • Replies: 3
    • Views: 376
    June 20th, 2017, 12:22 AM Go to last post
  16. USB Blaster II not recognized in CentOS 7

    Started by henriqa, April 27th, 2017 09:45 AM
    centos, linux, usb blaster
    • Replies: 3
    • Views: 706
    June 19th, 2017, 08:03 AM Go to last post
  17. No hardware in quartus programmer

    Started by ricardoluz, January 30th, 2017 03:22 AM
    blaster, issues, quartus, windows 10
    • Replies: 7
    • Views: 1,055
    June 19th, 2017, 12:38 AM Go to last post
  18. How to speedup the compilation of Quartus II

    Started by Haoxinyu, June 16th, 2017 11:35 PM
    • Replies: 5
    • Views: 456
    June 17th, 2017, 01:29 PM Go to last post
  19. Single multiplier takes up a whole DSP block for

    Started by shaiko, June 9th, 2017 01:22 PM
    • Replies: 3
    • Views: 529
    June 15th, 2017, 12:49 AM Go to last post
  20. VHDL inout port in gate-level simulation

    Started by maxvenum, June 13th, 2017 03:15 PM
    • Replies: 4
    • Views: 343
    June 14th, 2017, 12:10 PM Go to last post
  21. DDR same edge transfers VS opposite edge transfers

    Started by vlrean, June 14th, 2017 05:38 AM
    • Replies: 2
    • Views: 260
    June 14th, 2017, 10:40 AM Go to last post
    • Replies: 0
    • Views: 263
    June 12th, 2017, 04:20 AM Go to last post
  22. Random results in timing closure

    Started by pieter3d, June 11th, 2017 09:32 PM
    • Replies: 3
    • Views: 378
    June 12th, 2017, 01:07 AM Go to last post
  23. Question Error (12006): Node instance

    Started by kris222, June 11th, 2017 09:02 AM
    • Replies: 2
    • Views: 270
    June 11th, 2017, 11:26 PM Go to last post

Thread Display Options

Use this control to limit the display of threads to those newer than the specified time frame.

Allows you to choose the data by which the thread list will be sorted.

Order threads in...

Note: when sorting by date, 'descending order' will show the newest results first.

Icon Legend

Contains unread posts
Contains unread posts
Contains no unread posts
Contains no unread posts
More than 15 replies or 150 views
Hot thread with unread posts
More than 15 replies or 150 views
Hot thread with no unread posts
Closed Thread
Thread is closed
Thread Contains a Message Written By You
You have posted in this thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •