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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. Problems with Quartus Prime 16.1 Lite Edition

    Started by nabilsolo, February 24th, 2017 10:23 AM
    2 Pages
    1 2
    quartus
    • Replies: 13
    • Views: 126
    Yesterday, 04:59 PM Go to last post
  2. Who wins VERILOG_MACRO.qsf or `define.v?

    Started by systom, February 24th, 2017 04:53 PM
    verilog_macro
    • Replies: 7
    • Views: 100
    Yesterday, 04:17 PM Go to last post
  3. Quartus Prime Lite limitaions

    Started by Balasubrahmanya, February 22nd, 2017 10:27 PM
    • Replies: 4
    • Views: 119
    Yesterday, 12:30 PM Go to last post
  4. Need to write timing constraints for PLL generated clocks?

    Started by tcachat, January 27th, 2017 06:55 AM
    pll, sdc, timing contraints
    • Replies: 4
    • Views: 182
    Yesterday, 11:25 AM Go to last post
  5. BoardTestSystem.exe hang with no response

    Started by greglang, February 25th, 2017 05:00 AM
    • Replies: 1
    • Views: 45
    Yesterday, 11:19 AM Go to last post
    • Replies: 0
    • Views: 29
    Yesterday, 05:40 AM Go to last post
    • Replies: 1
    • Views: 65
    Yesterday, 02:04 AM Go to last post
  6. Same VHDL block RAM inferring file, different results

    Started by ozne, February 12th, 2017 07:42 PM
    block ram, quartus, ram inference, vhdl
    • Replies: 9
    • Views: 236
    February 26th, 2017, 12:18 AM Go to last post
  7. SignalTap II: can't add Master Time Bar in Quartus Prime 15.1

    Started by Pavel_47, February 25th, 2017 03:35 AM
    • Replies: 1
    • Views: 55
    February 25th, 2017, 05:40 PM Go to last post
  8. qsys, Pcie Ip Compiler

    Started by sirbabak, February 25th, 2017 10:32 AM
    gen2, pcie, qsys
    • Replies: 0
    • Views: 45
    February 25th, 2017, 10:32 AM Go to last post
  9. Quartus prime 16.1 and precision rtl 2016.2

    Started by thieulam, February 24th, 2017 12:19 AM
    • Replies: 0
    • Views: 41
    February 24th, 2017, 12:19 AM Go to last post
  10. Simulation fails if Modelsim time resolution is not 1ps

    Started by corestar, February 19th, 2017 06:37 PM
    • Replies: 4
    • Views: 142
    February 23rd, 2017, 01:49 PM Go to last post
  11. USB Blaster driver and Windows 10 issue (BSoDs)

    Started by akurczyk, February 17th, 2017 01:49 PM
    • Replies: 1
    • Views: 88
    February 23rd, 2017, 02:22 AM Go to last post
    • Replies: 0
    • Views: 49
    February 22nd, 2017, 02:04 PM Go to last post
  12. SDC constraints: One GCLK with two net names.

    Started by jimmymc, February 21st, 2017 10:57 AM
    sdc clock constraint
    • Replies: 5
    • Views: 134
    February 22nd, 2017, 11:43 AM Go to last post
  13. SignalTap II issue

    Started by Pavel_47, February 13th, 2017 07:27 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 297
    February 22nd, 2017, 11:17 AM Go to last post
  14. SDRAM Controller will be dropped from Quartus Lite!!

    Started by ep1015, January 19th, 2017 02:21 AM
    • Replies: 4
    • Views: 250
    February 22nd, 2017, 08:04 AM Go to last post
    • Replies: 0
    • Views: 40
    February 22nd, 2017, 07:58 AM Go to last post
    • Replies: 5
    • Views: 168
    February 22nd, 2017, 01:17 AM Go to last post
    • Replies: 2
    • Views: 135
    February 21st, 2017, 09:49 PM Go to last post
  15. Exclamation [Qsys] LPDDR2 Controller (UniPHY): HDL generation fails.

    Started by pctosi, February 13th, 2017 10:44 AM
    error, lpddr2, qsys, uniphy
    • Replies: 6
    • Views: 188
    February 21st, 2017, 02:51 AM Go to last post
  16. Quartus Prime Error: pin name is an illegal or unsupported format

    Started by john7, February 19th, 2017 08:04 AM
    • Replies: 0
    • Views: 93
    February 19th, 2017, 08:04 AM Go to last post
  17. secure mode in lite edition

    Started by idoyamar, February 19th, 2017 02:38 AM
    • Replies: 0
    • Views: 64
    February 19th, 2017, 02:38 AM Go to last post
  18. Question Issue with DE2-115 and Terasic Multi-Touch LCD

    Started by trustyhardware, June 16th, 2015 06:02 PM
    license
    • Replies: 2
    • Views: 894
    February 19th, 2017, 01:56 AM Go to last post
  19. SDC set_input_delay and set_output_delay constraints

    Started by dgal0215, August 2nd, 2013 01:34 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 31,226
    February 18th, 2017, 04:10 AM Go to last post
  20. Quartus Prime 16.1 - Timing simulation error .sdf file

    Started by RobertLyle, January 19th, 2017 01:04 AM
    • Replies: 1
    • Views: 208
    February 17th, 2017, 08:35 PM Go to last post
    • Replies: 1
    • Views: 88
    February 16th, 2017, 04:53 PM Go to last post
    • Replies: 6
    • Views: 175
    February 16th, 2017, 04:52 AM Go to last post
  21. How to constrain HPS I2C Bus?

    Started by kmorfitt, February 16th, 2017 03:06 AM
    • Replies: 0
    • Views: 80
    February 16th, 2017, 03:06 AM Go to last post
  22. Unable to connect to Quartus II Programmer JTAG Server

    Started by lukas, April 20th, 2011 05:10 AM
    • Replies: 3
    • Views: 35,663
    February 16th, 2017, 12:46 AM Go to last post

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