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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

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    Today, 10:18 AM Go to last post
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    Today, 07:02 AM Go to last post
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  1. Which licenses do I have checked out?

    Started by sadilek, December 14th, 2017 06:37 AM
    license, quartus 2
    • Replies: 1
    • Views: 139
    Yesterday, 10:53 AM Go to last post
  2. Wherer does Quartus put files?

    Started by Doug314, December 14th, 2017 08:53 AM
    • Replies: 4
    • Views: 186
    Yesterday, 08:11 AM Go to last post
  3. Print TDO on JTAG Chain Debugger

    Started by dams0622, Yesterday 02:01 AM
    • Replies: 0
    • Views: 101
    Yesterday, 02:01 AM Go to last post
  4. How to resolve this error?

    Started by Jerry, December 13th, 2017 07:20 PM
    • Replies: 2
    • Views: 192
    December 14th, 2017, 05:31 PM Go to last post
  5. Driver problem

    Started by Binome, December 14th, 2017 07:36 AM
    • Replies: 0
    • Views: 112
    December 14th, 2017, 07:36 AM Go to last post
  6. warning with on chip memory data items width

    Started by calagan, July 23rd, 2009 03:00 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 62,582
    December 13th, 2017, 08:51 AM Go to last post
  7. Cyclone 2 starter kit files

    Started by Gal13_private, December 11th, 2017 12:54 PM
    • Replies: 4
    • Views: 235
    December 12th, 2017, 01:15 PM Go to last post
  8. QuestaSim license usable in for ModelSim-altera

    Started by wobbert, December 11th, 2017 07:07 AM
    license, modelsim, questasim
    • Replies: 6
    • Views: 268
    December 12th, 2017, 11:09 AM Go to last post
  9. Warning: Tri-state nodes do not directly drive top-level pins

    Started by 888rt, December 11th, 2017 04:25 PM
    • Replies: 1
    • Views: 180
    December 11th, 2017, 04:44 PM Go to last post
    • Replies: 2
    • Views: 322
    December 10th, 2017, 01:17 AM Go to last post
  10. VHDL inout port in gate-level simulation

    Started by maxvenum, June 13th, 2017 04:15 PM
    • Replies: 5
    • Views: 1,318
    December 8th, 2017, 09:37 AM Go to last post
  11. Introducing delay in output pin

    Started by atrajesh, December 6th, 2017 02:49 AM
    • Replies: 9
    • Views: 462
    December 8th, 2017, 06:08 AM Go to last post
  12. How to ensure proper simulation in ModelSim

    Started by C1Ron, December 8th, 2017 01:25 AM
    • Replies: 6
    • Views: 376
    December 8th, 2017, 05:38 AM Go to last post
    • Replies: 0
    • Views: 163
    December 7th, 2017, 02:45 PM Go to last post
  13. Error when generating JESD204B Design EXample

    Started by alex-huang, December 7th, 2017 11:55 AM
    • Replies: 0
    • Views: 154
    December 7th, 2017, 11:55 AM Go to last post
    • Replies: 1
    • Views: 210
    December 7th, 2017, 10:50 AM Go to last post
  14. jtag debugger dosen't finds the connected cyclon ll processor

    Started by vrutha, December 1st, 2017 11:37 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 661
    December 7th, 2017, 03:02 AM Go to last post
  15. assign two clocks

    Started by Binome, November 30th, 2017 01:31 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 773
    December 6th, 2017, 11:47 PM Go to last post
  16. DDR differential pin assignments

    Started by Y0tsuya, December 4th, 2017 04:12 PM
    • Replies: 1
    • Views: 267
    December 5th, 2017, 06:05 PM Go to last post
  17. Cyclone V WYSIWYG primtives are broken :-(

    Started by lundril, July 28th, 2015 09:30 AM
    cyclone v, ddr3, wysiwyg
    • Replies: 4
    • Views: 2,482
    December 5th, 2017, 02:44 PM Go to last post
  18. Post PLL Simulation not working fine

    Started by XYZ, October 23rd, 2017 12:18 AM
    • Replies: 3
    • Views: 463
    December 5th, 2017, 12:59 AM Go to last post
    • Replies: 2
    • Views: 1,135
    December 5th, 2017, 12:56 AM Go to last post
  19. modelsim clock network stuck StX (gate level sim)

    Started by pmiach, December 3rd, 2017 03:07 AM
    • Replies: 6
    • Views: 381
    December 4th, 2017, 03:52 AM Go to last post
  20. TimeQuest Passes Hardware Fails

    Started by bangarren, December 3rd, 2017 11:40 PM
    • Replies: 0
    • Views: 243
    December 3rd, 2017, 11:40 PM Go to last post
  21. Neural Network

    Started by mohkredi, December 3rd, 2017 10:25 AM
    • Replies: 1
    • Views: 269
    December 3rd, 2017, 11:24 PM Go to last post
  22. how to dump routing elements in Quartus II

    Started by parcompute, April 13th, 2012 10:13 AM
    • Replies: 6
    • Views: 36,685
    December 1st, 2017, 04:23 PM Go to last post
  23. TIMEQUEST: possible to do in the SDC ?....

    Started by berretto77, December 1st, 2017 04:40 AM
    • Replies: 0
    • Views: 256
    December 1st, 2017, 04:40 AM Go to last post

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