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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. Quartus II Programmer - Command Line

    Started by BillMed1, July 19th, 2017 07:44 AM
    • Replies: 6
    • Views: 213
    Yesterday, 10:04 AM Go to last post
  2. connecting to quartus

    Started by seongjinkim, July 20th, 2017 04:42 AM
    • Replies: 4
    • Views: 110
    Yesterday, 09:41 AM Go to last post
  3. How to simulate an inertial delay in ModelSim?

    Started by CoxJacob, February 2nd, 2013 02:21 PM
    2 Pages
    1 2
    • Replies: 17
    • Views: 32,387
    Yesterday, 08:45 AM Go to last post
  4. Question Timequest default setup relationship through PLLs

    Started by bangarren, July 19th, 2017 10:42 PM
    • Replies: 4
    • Views: 149
    Yesterday, 04:21 AM Go to last post
  5. Unused VHDL entity ports in Quartus

    Started by shaiko, July 20th, 2017 12:25 AM
    • Replies: 1
    • Views: 73
    July 20th, 2017, 01:34 AM Go to last post
  6. Question Quartus internal bus tool

    Started by seongjinkim, July 19th, 2017 09:12 PM
    bus tool, chip scope, quartus
    • Replies: 4
    • Views: 106
    July 20th, 2017, 01:15 AM Go to last post
    • Replies: 0
    • Views: 54
    July 19th, 2017, 11:18 PM Go to last post
  7. Verilog simulation model for ncverilog and ncsim

    Started by peter.chang, July 19th, 2017 09:02 PM
    • Replies: 0
    • Views: 55
    July 19th, 2017, 09:02 PM Go to last post
  8. Question Timequest Timing Problems

    Started by yonghang, July 19th, 2017 07:20 AM
    quartus, timequest
    • Replies: 1
    • Views: 113
    July 19th, 2017, 07:28 AM Go to last post
  9. Importing EDIF To Quartus project

    Started by studentAltera, July 18th, 2017 03:41 PM
    • Replies: 1
    • Views: 125
    July 19th, 2017, 02:51 AM Go to last post
  10. Quartus II V16: .sdo files not generated

    Started by tezhi, July 18th, 2017 06:48 PM
    • Replies: 0
    • Views: 105
    July 18th, 2017, 06:48 PM Go to last post
  11. Cannot Add new License

    Started by Pdonegan, July 18th, 2017 01:51 PM
    • Replies: 0
    • Views: 103
    July 18th, 2017, 01:51 PM Go to last post
  12. Can't link device to design in System Console

    Started by Rayho, January 18th, 2017 01:25 AM
    • Replies: 2
    • Views: 533
    July 18th, 2017, 06:20 AM Go to last post
  13. Quartus 17 JBC Files & STAPL Player @ MAX10

    Started by tiano, May 16th, 2017 12:22 AM
    jam jbc stapl
    • Replies: 1
    • Views: 467
    July 17th, 2017, 05:28 PM Go to last post
    • Replies: 0
    • Views: 132
    July 17th, 2017, 02:00 PM Go to last post
  14. Question Quartus II: Error(10777)

    Started by MMalik, June 2nd, 2010 12:00 AM
    • Replies: 3
    • Views: 33,778
    July 17th, 2017, 12:02 PM Go to last post
  15. Simulation using University program stuck

    Started by m.zerafa, July 17th, 2017 10:29 AM
    • Replies: 0
    • Views: 115
    July 17th, 2017, 10:29 AM Go to last post
  16. Maximum width of FIFO

    Started by shaiko, July 16th, 2017 12:58 PM
    • Replies: 2
    • Views: 197
    July 16th, 2017, 01:30 PM Go to last post
  17. TTL and CMOS ICs famiies in schematic design

    Started by MacGab997, July 16th, 2017 01:43 AM
    • Replies: 2
    • Views: 220
    July 16th, 2017, 08:35 AM Go to last post
  18. Weird SignalTap behaviour

    Started by justintime, November 24th, 2016 09:15 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 2,150
    July 15th, 2017, 02:05 AM Go to last post
  19. Streaming Packet Signal Errors

    Started by ArcticRain, July 14th, 2017 12:41 PM
    • Replies: 1
    • Views: 201
    July 14th, 2017, 09:41 PM Go to last post
  20. Possible places for Pin assignments for a design

    Started by poornacs, July 12th, 2017 06:53 AM
    fitter location, pin assignments, pin lock, pin planner, place and route
    • Replies: 2
    • Views: 244
    July 12th, 2017, 07:41 AM Go to last post
  21. Error:invalid command name "quartus_sh"

    Started by felixipg, July 12th, 2017 05:00 AM
    • Replies: 1
    • Views: 203
    July 12th, 2017, 06:52 AM Go to last post
  22. Question Where is the Signaltap JTAG usb driver documentation ?

    Started by alexis57, July 9th, 2017 03:47 PM
    • Replies: 4
    • Views: 420
    July 11th, 2017, 01:10 PM Go to last post
  23. Question Q14.1 web edition Alt_sld_fab problem

    Started by owts9999, March 26th, 2015 12:49 AM
    • Replies: 1
    • Views: 2,914
    July 11th, 2017, 12:07 PM Go to last post
  24. in system memory content editor

    Started by bassem yasser, July 8th, 2017 04:40 PM
    • Replies: 2
    • Views: 337
    July 10th, 2017, 11:40 AM Go to last post
  25. Angry customized component got overwriten

    Started by eaglepeng, July 6th, 2017 07:48 AM
    qsys component overwrite
    • Replies: 5
    • Views: 469
    July 10th, 2017, 07:36 AM Go to last post
  26. hold timing and clock frequency considerations

    Started by idoyamar, July 9th, 2017 11:21 AM
    • Replies: 6
    • Views: 621
    July 10th, 2017, 03:26 AM Go to last post
  27. ALT_SLD_FAB Errors

    Started by buyukdegirmenci, July 9th, 2017 06:08 AM
    alt_sld_fab, design_hash, emoduleproperty, nios, sld_hub
    • Replies: 2
    • Views: 334
    July 9th, 2017, 10:26 PM Go to last post
  28. QSYS simulation using Avalon-MM BFM

    Started by CaptainJack, July 9th, 2017 06:34 AM
    • Replies: 1
    • Views: 263
    July 9th, 2017, 09:22 PM Go to last post

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