Page 1 of 15 12311 ... LastLast
Threads 1 to 30 of 449

Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,126
    October 5th, 2012, 12:48 PM Go to last post
  1. Verilog examples wanted.

    Started by pdped, Today 07:57 AM
    • Replies: 0
    • Views: 24
    Today, 07:57 AM Go to last post
  2. verilog code for serial in parallel out shift register

    Started by ecasha, March 2nd, 2017 12:33 AM
    verilog, vhdl
    • Replies: 2
    • Views: 205
    March 27th, 2017, 04:51 PM Go to last post
  3. How to export signals from a UART (TX,RX) in verilog

    Started by riverrock, March 1st, 2017 01:33 AM
    • Replies: 4
    • Views: 241
    March 25th, 2017, 12:24 AM Go to last post
    • Replies: 1
    • Views: 660
    March 10th, 2017, 02:57 AM Go to last post
  4. AXI to AHB Bridge

    Started by susharma, March 9th, 2017 09:57 PM
    • Replies: 0
    • Views: 107
    March 9th, 2017, 09:57 PM Go to last post
  5. Connect split bus in verilog to output

    Started by rozsatib, March 5th, 2017 11:17 PM
    • Replies: 2
    • Views: 190
    March 6th, 2017, 01:13 AM Go to last post
  6. Bist code for integer based arithmetic and logical operation

    Started by r25upase, February 9th, 2017 10:37 PM
    • Replies: 3
    • Views: 315
    February 10th, 2017, 10:14 AM Go to last post
  7. Verilog ModelSim beginner Hello

    Started by juwho, February 6th, 2017 08:18 PM
    modelsim, student
    • Replies: 1
    • Views: 214
    February 7th, 2017, 03:10 AM Go to last post
  8. Instantiating VHDL entities into a Verilog top level

    Started by Pdonegan, February 1st, 2017 10:27 AM
    • Replies: 2
    • Views: 266
    February 2nd, 2017, 04:51 AM Go to last post
    • Replies: 1
    • Views: 310
    January 29th, 2017, 11:07 AM Go to last post
    • Replies: 2
    • Views: 303
    January 23rd, 2017, 02:54 AM Go to last post
  9. Generate Case Instantiation

    Started by roger8144, January 20th, 2017 05:49 AM
    • Replies: 5
    • Views: 340
    January 20th, 2017, 07:33 AM Go to last post
    • Replies: 1
    • Views: 683
    January 14th, 2017, 06:17 AM Go to last post
  10. Using PLL "lock" signal as the async reset in Verilog

    Started by buddha1987, January 2nd, 2014 02:10 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 25,056
    January 6th, 2017, 01:35 PM Go to last post
  11. Question How to generate Global RESET signal in Verilog?

    Started by knowfish, August 12th, 2016 01:42 AM
    2 Pages
    1 2
    asynchronous reset, fpga reset, reset signal generation, synchronous reset
    • Replies: 11
    • Views: 1,759
    January 4th, 2017, 04:17 AM Go to last post
  12. basic always block question

    Started by Numinus1, January 2nd, 2017 12:09 AM
    • Replies: 1
    • Views: 259
    January 2nd, 2017, 01:18 AM Go to last post
  13. MegaWizard 2x8k Dual Port Memory

    Started by HarryPothead, November 19th, 2016 07:01 AM
    • Replies: 4
    • Views: 572
    November 26th, 2016, 05:14 AM Go to last post
    • Replies: 0
    • Views: 332
    November 8th, 2016, 02:09 PM Go to last post
  14. Pseudo Random Bit Sequence Verilog

    Started by SumeetB, October 5th, 2016 01:56 PM
    bit sequence, spf+, stratix v, verilog
    • Replies: 3
    • Views: 699
    November 7th, 2016, 09:11 AM Go to last post
  15. TSW1400EVM / Altera Stratix IV / PLL replacement

    Started by ZEZE, July 20th, 2016 02:30 AM
    altera stratix iv, pll replacement, tsw1400evm
    • Replies: 5
    • Views: 883
    November 6th, 2016, 09:19 PM Go to last post
  16. DE2-70 Stereo vision

    Started by TSchokker, May 26th, 2016 03:33 AM
    camera, de2-70, disparity, disparity map, stereo vision
    • Replies: 1
    • Views: 653
    November 3rd, 2016, 06:42 AM Go to last post
    • Replies: 3
    • Views: 485
    October 31st, 2016, 02:28 PM Go to last post
    • Replies: 3
    • Views: 480
    October 31st, 2016, 06:25 AM Go to last post
  17. Red face The numbers stored in memory in verilog

    Started by faramarzsy, October 13th, 2016 11:25 PM
    • Replies: 0
    • Views: 401
    October 13th, 2016, 11:25 PM Go to last post
  18. reg [ x +: 12] mean ?

    Started by kavinda, October 6th, 2016 01:07 AM
    • Replies: 2
    • Views: 488
    October 6th, 2016, 07:31 AM Go to last post
  19. Array Elements and Indexing

    Started by kavinda, October 5th, 2016 05:13 PM
    • Replies: 2
    • Views: 486
    October 5th, 2016, 11:29 PM Go to last post
  20. Assigning pins in DE2 115

    Started by varunme, March 26th, 2013 11:13 PM
    • Replies: 8
    • Views: 34,714
    October 4th, 2016, 11:36 PM Go to last post
    • Replies: 5
    • Views: 1,022
    October 4th, 2016, 03:50 AM Go to last post
  21. Quartus reports:can't pass value from actual to argument xxx.

    Started by Mr.John, September 27th, 2016 12:45 AM
    systemverilog
    • Replies: 3
    • Views: 679
    September 30th, 2016, 01:21 AM Go to last post
  22. Quartus reports:can't pass value from actual to argument xxx.

    Started by Mr.John, September 27th, 2016 12:39 AM
    systemverilog
    • Replies: 0
    • Views: 294
    September 27th, 2016, 12:39 AM Go to last post

Thread Display Options

Use this control to limit the display of threads to those newer than the specified time frame.

Allows you to choose the data by which the thread list will be sorted.

Order threads in...

Note: when sorting by date, 'descending order' will show the newest results first.

Icon Legend

Contains unread posts
Contains unread posts
Contains no unread posts
Contains no unread posts
More than 15 replies or 150 views
Hot thread with unread posts
More than 15 replies or 150 views
Hot thread with no unread posts
Closed Thread
Thread is closed
Thread Contains a Message Written By You
You have posted in this thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •