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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 41,576
    October 5th, 2012, 12:48 PM Go to last post
    • Replies: 0
    • Views: 1
    Today, 08:37 PM Go to last post
    • Replies: 2
    • Views: 36
    Today, 08:16 PM Go to last post
  1. Question 10 tap fir filter in verilog

    Started by soorajs, Yesterday 02:21 AM
    • Replies: 5
    • Views: 87
    Today, 03:43 PM Go to last post
  2. Counter, synthesize problems

    Started by adacho94, August 19th, 2016 10:47 AM
    • Replies: 1
    • Views: 106
    August 22nd, 2016, 02:50 AM Go to last post
  3. Lightbulb Request of feedback on SPI Slave moduel

    Started by zehortigoza, August 18th, 2016 02:07 PM
    max10, slave, spi
    • Replies: 2
    • Views: 61
    August 19th, 2016, 06:11 AM Go to last post
  4. Question How to generate Global RESET signal in Verilog?

    Started by knowfish, August 12th, 2016 01:42 AM
    asynchronous reset, fpga reset, reset signal generation, synchronous reset
    • Replies: 4
    • Views: 179
    August 15th, 2016, 08:06 PM Go to last post
    • Replies: 10
    • Views: 183
    August 15th, 2016, 04:32 AM Go to last post
  5. inout wire logic, quartus15.1, error

    Started by putnik47, July 28th, 2016 08:04 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 219
    August 12th, 2016, 02:37 AM Go to last post
  6. Question Curly braces

    Started by djp, August 11th, 2016 02:31 AM
    concatenation operator
    • Replies: 3
    • Views: 134
    August 11th, 2016, 08:45 PM Go to last post
    • Replies: 3
    • Views: 231
    August 3rd, 2016, 09:06 AM Go to last post
  7. Verilog code

    Started by gzbec040, July 22nd, 2016 10:18 PM
    • Replies: 1
    • Views: 217
    July 23rd, 2016, 02:26 AM Go to last post
  8. Implementing firmware version

    Started by Caliri, December 4th, 2012 01:28 AM
    3 Pages
    1 2 3
    • Replies: 22
    • Views: 32,845
    July 21st, 2016, 12:20 AM Go to last post
  9. TSW1400EVM / Altera Stratix IV / PLL replacement

    Started by ZEZE, July 20th, 2016 02:30 AM
    altera stratix iv, pll replacement, tsw1400evm
    • Replies: 4
    • Views: 193
    July 20th, 2016, 07:41 AM Go to last post
  10. Assigning pins in DE2 115

    Started by varunme, March 26th, 2013 11:13 PM
    • Replies: 7
    • Views: 32,868
    July 17th, 2016, 02:21 PM Go to last post
    • Replies: 4
    • Views: 296
    July 13th, 2016, 07:49 AM Go to last post
    • Replies: 13
    • Views: 320
    July 12th, 2016, 07:52 AM Go to last post
  11. Guidelines to avoid Negative Slack with State Machines

    Started by jeebujacob, June 29th, 2016 01:06 AM
    2 Pages
    1 2
    negative slack, setup violation, timing closure
    • Replies: 11
    • Views: 559
    July 10th, 2016, 08:32 PM Go to last post
  12. identifier error 10734

    Started by tolu, July 7th, 2016 11:04 AM
    • Replies: 1
    • Views: 166
    July 8th, 2016, 12:27 AM Go to last post
  13. Verilog Assignment

    Started by nanostallmann, July 6th, 2016 10:51 AM
    • Replies: 2
    • Views: 199
    July 6th, 2016, 12:36 PM Go to last post
  14. Module Instantiation Problem

    Started by faraz240, June 27th, 2016 08:05 PM
    • Replies: 2
    • Views: 201
    June 28th, 2016, 12:53 PM Go to last post
  15. Red face Difference between simulation and real test.

    Started by mrquan1506, June 19th, 2016 01:22 AM
    • Replies: 2
    • Views: 216
    June 22nd, 2016, 01:57 AM Go to last post
    • Replies: 4
    • Views: 421
    June 22nd, 2016, 01:43 AM Go to last post
  16. How to interface my verilog code with FFT ip core

    Started by mws000, June 15th, 2016 06:23 AM
    • Replies: 1
    • Views: 203
    June 20th, 2016, 05:45 AM Go to last post
  17. Post resistor capacitor

    Started by Chris7, June 6th, 2016 12:38 AM
    • Replies: 1
    • Views: 282
    June 7th, 2016, 04:34 AM Go to last post
  18. packages for synthesis

    Started by Shempington, June 2nd, 2016 10:14 AM
    package, synthesis, systemverilog
    • Replies: 1
    • Views: 268
    June 6th, 2016, 04:05 AM Go to last post
  19. Memory coding style

    Started by hdecharn, May 28th, 2016 02:07 AM
    • Replies: 5
    • Views: 380
    May 29th, 2016, 08:10 AM Go to last post
  20. Error 12007.

    Started by tolu, May 27th, 2016 01:56 PM
    • Replies: 1
    • Views: 234
    May 28th, 2016, 12:37 AM Go to last post
  21. DE2-70 Stereo vision

    Started by TSchokker, May 26th, 2016 03:33 AM
    camera, de2-70, disparity, disparity map, stereo vision
    • Replies: 0
    • Views: 213
    May 26th, 2016, 03:33 AM Go to last post
    • Replies: 3
    • Views: 305
    May 25th, 2016, 10:38 AM Go to last post
    • Replies: 0
    • Views: 237
    May 19th, 2016, 05:35 AM Go to last post

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