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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 44,507
    October 5th, 2012, 12:48 PM Go to last post
  1. Need help in realizing a simple clock

    Started by bcao3, May 8th, 2014 08:51 AM
    • Replies: 3
    • Views: 15,650
    May 15th, 2014, 01:58 AM Go to last post
  2. First verilog project

    Started by JHEnt, April 20th, 2014 07:57 PM
    • Replies: 9
    • Views: 21,344
    May 12th, 2014, 06:07 AM Go to last post
  3. May I use a reg variable to indicate the bus bit ?

    Started by buddha1987, May 5th, 2014 10:45 AM
    • Replies: 6
    • Views: 16,216
    May 6th, 2014, 07:33 AM Go to last post
    • Replies: 3
    • Views: 15,885
    May 5th, 2014, 09:41 AM Go to last post
  4. The question about bidirectional port

    Started by buddha1987, May 2nd, 2014 01:05 PM
    • Replies: 1
    • Views: 16,298
    May 2nd, 2014, 01:29 PM Go to last post
  5. Synthesis of non-blocking statements

    Started by OutputLogic, April 30th, 2014 10:58 PM
    non-blocking, verilog
    • Replies: 3
    • Views: 16,595
    May 1st, 2014, 05:58 PM Go to last post
  6. Question on posedge in always block

    Started by rob18767, April 25th, 2014 12:17 PM
    • Replies: 9
    • Views: 19,851
    April 29th, 2014, 07:33 AM Go to last post
  7. how to use `timescale in verilog!

    Started by dinhngoclambk, April 19th, 2014 05:54 PM
    • Replies: 4
    • Views: 20,014
    April 26th, 2014, 02:28 AM Go to last post
    • Replies: 6
    • Views: 17,220
    April 23rd, 2014, 07:43 AM Go to last post
  8. stepper motor

    Started by tjrobertson22257, April 8th, 2014 05:09 AM
    • Replies: 0
    • Views: 17,330
    April 8th, 2014, 05:09 AM Go to last post
    • Replies: 0
    • Views: 17,688
    April 7th, 2014, 10:00 PM Go to last post
  9. Hearts Card Game in Verilog

    Started by tabish_ayub, April 6th, 2014 10:41 PM
    verilog
    • Replies: 1
    • Views: 16,567
    April 7th, 2014, 07:14 AM Go to last post
  10. edge detection in verilog,. help

    Started by imaroj, April 5th, 2014 09:14 PM
    • Replies: 2
    • Views: 18,513
    April 6th, 2014, 09:30 AM Go to last post
  11. transmission gate with pmos and nmos

    Started by eng4ever, April 2nd, 2014 05:52 AM
    cmos, nmos, pmos, quartus, verilog
    • Replies: 3
    • Views: 18,118
    April 5th, 2014, 12:43 PM Go to last post
  12. Question [SystemVerilog] Passing "inout" thru verbatim

    Started by Cyclone User, March 25th, 2014 02:00 PM
    inout, systemverilog
    • Replies: 2
    • Views: 19,326
    March 25th, 2014, 03:26 PM Go to last post
  13. speech recognition system

    Started by cz_21, March 24th, 2014 05:41 AM
    ann, audio, fft, fpga, mfcc
    • Replies: 6
    • Views: 19,787
    March 25th, 2014, 06:55 AM Go to last post
  14. Post counter

    Started by mdagne, March 23rd, 2014 08:12 PM
    • Replies: 1
    • Views: 18,248
    March 24th, 2014, 06:17 AM Go to last post
  15. Post FATAL ERROR while loading design "# Error loading design"

    Started by Rishi, March 20th, 2014 10:09 AM
    • Replies: 1
    • Views: 19,083
    March 24th, 2014, 06:13 AM Go to last post
  16. "gating" one process from another

    Started by richas, March 20th, 2014 08:49 AM
    • Replies: 1
    • Views: 17,637
    March 21st, 2014, 04:08 AM Go to last post
    • Replies: 1
    • Views: 17,581
    March 20th, 2014, 06:21 AM Go to last post
  17. Output bit stream

    Started by richas, March 19th, 2014 10:32 AM
    • Replies: 0
    • Views: 17,428
    March 19th, 2014, 10:32 AM Go to last post
  18. Read from sd card an image on DE2-115

    Started by anthimos, October 25th, 2013 02:21 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 34,700
    March 18th, 2014, 01:23 AM Go to last post
  19. tree structure

    Started by eva, February 24th, 2014 09:12 PM
    • Replies: 2
    • Views: 18,780
    March 16th, 2014, 03:08 AM Go to last post
  20. "VGA display" problem on DE2 board - Only 1 color on screen :(

    Started by bao09, December 29th, 2012 07:02 AM
    • Replies: 4
    • Views: 38,103
    March 14th, 2014, 04:25 PM Go to last post
  21. About logic and with bitwise and

    Started by buddha1987, March 13th, 2014 11:30 AM
    • Replies: 1
    • Views: 17,713
    March 13th, 2014, 10:37 PM Go to last post
  22. verlog code error

    Started by nisu, March 6th, 2014 07:16 PM
    • Replies: 2
    • Views: 17,944
    March 7th, 2014, 01:41 AM Go to last post
  23. Warning (15610): No output dependent on input pin

    Started by Abdulla873, February 26th, 2014 06:22 PM
    • Replies: 6
    • Views: 22,689
    February 28th, 2014, 12:28 PM Go to last post
  24. Signal related problem ----Stop the output (Urgent)

    Started by samsam0407, February 27th, 2014 12:41 AM
    • Replies: 4
    • Views: 17,812
    February 27th, 2014, 11:28 PM Go to last post
  25. Include file

    Started by Aflatoun, February 25th, 2014 11:44 AM
    • Replies: 1
    • Views: 17,815
    February 25th, 2014, 11:49 AM Go to last post
  26. SUm of table

    Started by Aflatoun, February 22nd, 2014 02:56 AM
    • Replies: 2
    • Views: 17,683
    February 25th, 2014, 11:41 AM Go to last post

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