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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 43,265
    October 5th, 2012, 12:48 PM Go to last post
  1. IIR filter implementation in verilog

    Started by mz5, January 30th, 2014 09:48 PM
    iir filter in verilog
    • Replies: 2
    • Views: 20,939
    January 31st, 2014, 01:00 AM Go to last post
  2. clock division in verilog

    Started by danilojcamara, January 30th, 2014 03:46 AM
    clock division, de2
    • Replies: 2
    • Views: 17,882
    January 30th, 2014, 01:10 PM Go to last post
  3. Beginner question about making a beep sound

    Started by samsam0407, January 17th, 2014 09:49 AM
    • Replies: 3
    • Views: 18,729
    January 27th, 2014, 12:06 AM Go to last post
  4. Generate Shapes using Verilog

    Started by hubakboy, January 25th, 2014 05:28 AM
    • Replies: 0
    • Views: 18,668
    January 25th, 2014, 05:28 AM Go to last post
    • Replies: 3
    • Views: 19,904
    January 24th, 2014, 01:10 PM Go to last post
    • Replies: 0
    • Views: 17,661
    January 21st, 2014, 03:58 AM Go to last post
  5. Syntax to conditionally assign integer or parameter

    Started by frog1600, January 3rd, 2014 06:53 AM
    • Replies: 1
    • Views: 21,254
    January 3rd, 2014, 07:40 AM Go to last post
    • Replies: 2
    • Views: 20,768
    December 27th, 2013, 08:57 AM Go to last post
  6. Unhappy Help!! sound sensor with cyclone IV

    Started by mayarelmohr, December 24th, 2013 05:17 AM
    • Replies: 0
    • Views: 19,425
    December 24th, 2013, 05:17 AM Go to last post
  7. Basics - 2 inputs, 1 output + positive edges

    Started by piotr.kozierski, December 20th, 2013 02:56 AM
    • Replies: 2
    • Views: 21,071
    December 20th, 2013, 06:09 AM Go to last post
  8. Need Help - Object Tracking

    Started by phyrdows, December 20th, 2013 06:04 AM
    • Replies: 0
    • Views: 19,845
    December 20th, 2013, 06:04 AM Go to last post
  9. how to combine verilog module

    Started by Fauzan Ramli, December 19th, 2013 10:49 PM
    • Replies: 0
    • Views: 20,481
    December 19th, 2013, 10:49 PM Go to last post
  10. Question Line out port de1 .. help !

    Started by fahad_r89, November 30th, 2013 06:25 AM
    • Replies: 1
    • Views: 20,680
    December 10th, 2013, 03:59 PM Go to last post
    • Replies: 2
    • Views: 23,728
    December 10th, 2013, 06:40 AM Go to last post
  11. Question Module parameters

    Started by yuuul, December 2nd, 2013 02:46 PM
    module, parameters, verilog
    • Replies: 1
    • Views: 21,807
    December 4th, 2013, 12:39 AM Go to last post
  12. verilog code about shift phase 0, 90, 180, 270

    Started by sean98007, November 28th, 2013 06:56 AM
    • Replies: 6
    • Views: 25,694
    December 2nd, 2013, 01:42 PM Go to last post
    • Replies: 0
    • Views: 24,586
    November 27th, 2013, 02:13 PM Go to last post
  13. help creating delay in fsm

    Started by phaeight, November 25th, 2013 07:16 PM
    • Replies: 0
    • Views: 22,639
    November 25th, 2013, 07:16 PM Go to last post
  14. Help with verilog testbench code

    Started by defeduma, November 21st, 2013 01:18 AM
    • Replies: 1
    • Views: 22,416
    November 25th, 2013, 02:31 AM Go to last post
  15. verilog testbench file in emacs verilog mode

    Started by tba109, November 22nd, 2013 05:53 AM
    • Replies: 2
    • Views: 21,946
    November 22nd, 2013, 10:36 AM Go to last post
  16. Verilog excess Three no out puts

    Started by frost785, November 13th, 2013 08:36 AM
    excess three, verilog, wrong outputs
    • Replies: 3
    • Views: 23,686
    November 14th, 2013, 09:17 AM Go to last post
  17. instantiating megafunctions

    Started by sparkyee, November 13th, 2013 11:40 AM
    • Replies: 1
    • Views: 21,028
    November 13th, 2013, 12:17 PM Go to last post
  18. Help making a timer

    Started by marty13612, November 9th, 2013 10:46 AM
    • Replies: 5
    • Views: 24,433
    November 10th, 2013, 07:08 PM Go to last post
  19. Simple syntax error

    Started by marty13612, November 2nd, 2013 09:42 AM
    • Replies: 2
    • Views: 24,101
    November 2nd, 2013, 10:13 AM Go to last post
  20. Help with internal Clock and States

    Started by marty13612, October 31st, 2013 06:51 PM
    • Replies: 3
    • Views: 23,908
    November 1st, 2013, 08:56 AM Go to last post
    • Replies: 2
    • Views: 24,110
    October 28th, 2013, 04:51 AM Go to last post
  21. verilog code for SINE PWM

    Started by shasikumar253, October 21st, 2013 10:12 PM
    sine pwm
    • Replies: 3
    • Views: 25,194
    October 22nd, 2013, 01:41 AM Go to last post
  22. How about a verilog case statement that covers a range?

    Started by buddha1987, September 16th, 2013 01:50 PM
    • Replies: 6
    • Views: 43,044
    October 21st, 2013, 07:25 AM Go to last post
  23. shift register structural modeling error with port

    Started by phaeight, October 18th, 2013 08:37 PM
    • Replies: 3
    • Views: 26,423
    October 19th, 2013, 04:41 AM Go to last post
  24. $readmemb task trouble

    Started by brokenheart1712, September 15th, 2013 07:53 PM
    • Replies: 3
    • Views: 29,049
    October 17th, 2013, 07:05 AM Go to last post

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