Page 11 of 15 FirstFirst ... 910111213 ... LastLast
Threads 301 to 330 of 448

Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,092
    October 5th, 2012, 12:48 PM Go to last post
  1. shift register structural modeling error with port

    Started by phaeight, October 18th, 2013 08:37 PM
    • Replies: 3
    • Views: 25,483
    October 19th, 2013, 04:41 AM Go to last post
  2. $readmemb task trouble

    Started by brokenheart1712, September 15th, 2013 07:53 PM
    • Replies: 3
    • Views: 28,297
    October 17th, 2013, 07:05 AM Go to last post
  3. Error: Top-level design entity "bai3" is undefined

    Started by phonghoa2008247, September 27th, 2013 06:04 AM
    • Replies: 3
    • Views: 27,031
    October 16th, 2013, 10:45 PM Go to last post
  4. how to write a counter? verilog~~~

    Started by KyoukaNg, October 13th, 2013 11:09 PM
    • Replies: 2
    • Views: 29,085
    October 16th, 2013, 10:34 PM Go to last post
  5. What is mean by output port has no driver???

    Started by KyoukaNg, October 13th, 2013 07:40 AM
    • Replies: 3
    • Views: 29,031
    October 16th, 2013, 12:22 AM Go to last post
  6. Good Book on SystemVerilog Primer for FPGAs?

    Started by JPL, July 4th, 2013 11:40 AM
    • Replies: 2
    • Views: 30,180
    October 15th, 2013, 12:04 PM Go to last post
  7. storing first set of values in a register

    Started by leelathimmaiah, October 9th, 2013 02:03 AM
    • Replies: 0
    • Views: 25,523
    October 9th, 2013, 02:03 AM Go to last post
  8. Connecting the ports of the tb and DUT

    Started by leelathimmaiah, October 1st, 2013 05:15 AM
    • Replies: 1
    • Views: 32,261
    October 3rd, 2013, 01:34 AM Go to last post
    • Replies: 1
    • Views: 28,166
    September 28th, 2013, 11:59 PM Go to last post
    • Replies: 6
    • Views: 29,792
    September 24th, 2013, 04:04 AM Go to last post
    • Replies: 3
    • Views: 28,089
    September 21st, 2013, 06:05 AM Go to last post
    • Replies: 9
    • Views: 28,811
    September 21st, 2013, 05:59 AM Go to last post
  9. Lightbulb interfacing of co2 sensor and zigbee with cyclone 4

    Started by muthukumaran, September 16th, 2013 10:01 PM
    co2 sensor, cyclone 4, temperature sensor, vhdl, zigbee
    • Replies: 3
    • Views: 29,073
    September 20th, 2013, 12:38 AM Go to last post
  10. How should I write Verilog to describe DDR?

    Started by buddha1987, September 17th, 2013 06:39 AM
    • Replies: 3
    • Views: 27,198
    September 18th, 2013, 11:08 AM Go to last post
  11. Zero Packed Or Unpacked Array Dimensions Problems

    Started by brokenheart1712, September 15th, 2013 10:43 AM
    • Replies: 1
    • Views: 28,457
    September 15th, 2013, 07:55 PM Go to last post
  12. Fully parallel architecture of LDPC decoder

    Started by sougata, September 14th, 2013 03:25 AM
    • Replies: 0
    • Views: 24,072
    September 14th, 2013, 03:25 AM Go to last post
    • Replies: 4
    • Views: 27,293
    September 12th, 2013, 07:37 AM Go to last post
  13. three stages for a shifter (shifting by 0~7 bits)

    Started by JenC, June 30th, 2013 08:08 PM
    • Replies: 4
    • Views: 34,192
    August 23rd, 2013, 11:56 AM Go to last post
  14. converting a signed shift amount to unsigned

    Started by JenC, July 4th, 2013 11:28 AM
    • Replies: 2
    • Views: 33,008
    August 22nd, 2013, 11:54 PM Go to last post
    • Replies: 1
    • Views: 31,989
    August 15th, 2013, 07:54 AM Go to last post
  15. Initialize parameter of an array type

    Started by kok-loong.cheah, August 1st, 2013 10:04 PM
    • Replies: 6
    • Views: 38,004
    August 5th, 2013, 06:04 PM Go to last post
  16. half-band filter implementation

    Started by JenC, July 27th, 2013 10:16 AM
    • Replies: 3
    • Views: 31,504
    July 27th, 2013, 01:05 PM Go to last post
  17. clock divider with counter

    Started by muzammil007, July 22nd, 2013 08:32 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 37,091
    July 25th, 2013, 03:15 PM Go to last post
  18. Systemverilog task inside class

    Started by htmin, July 24th, 2013 11:19 PM
    • Replies: 0
    • Views: 30,362
    July 24th, 2013, 11:19 PM Go to last post
  19. module instantiation

    Started by muzammil007, July 16th, 2013 09:04 AM
    • Replies: 5
    • Views: 31,334
    July 22nd, 2013, 05:56 PM Go to last post
  20. precision for a cos(x)/sin(x) lookup table

    Started by JenC, July 21st, 2013 09:59 AM
    • Replies: 4
    • Views: 30,862
    July 21st, 2013, 08:55 PM Go to last post
  21. calculator

    Started by mnasrr, July 20th, 2013 04:54 AM
    • Replies: 1
    • Views: 28,545
    July 21st, 2013, 12:31 PM Go to last post
  22. cos() function in Verilog

    Started by JenC, July 19th, 2013 12:36 AM
    • Replies: 3
    • Views: 32,469
    July 19th, 2013, 09:17 AM Go to last post
  23. speed of execution of a design with eliminated latches

    Started by JenC, July 16th, 2013 07:21 PM
    • Replies: 1
    • Views: 31,483
    July 17th, 2013, 03:05 PM Go to last post
    • Replies: 1
    • Views: 30,929
    July 16th, 2013, 11:39 PM Go to last post

Thread Display Options

Use this control to limit the display of threads to those newer than the specified time frame.

Allows you to choose the data by which the thread list will be sorted.

Order threads in...

Note: when sorting by date, 'descending order' will show the newest results first.

Icon Legend

Contains unread posts
Contains unread posts
Contains no unread posts
Contains no unread posts
More than 15 replies or 150 views
Hot thread with unread posts
More than 15 replies or 150 views
Hot thread with no unread posts
Closed Thread
Thread is closed
Thread Contains a Message Written By You
You have posted in this thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •