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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:48 PM
    • Replies: 0
    • Views: 44,026
    October 5th, 2012, 01:48 PM Go to last post
  1. speech recognition system

    Started by cz_21, March 24th, 2014 06:41 AM
    ann, audio, fft, fpga, mfcc
    • Replies: 6
    • Views: 19,618
    March 25th, 2014, 07:55 AM Go to last post
  2. Post counter

    Started by mdagne, March 23rd, 2014 09:12 PM
    • Replies: 1
    • Views: 18,185
    March 24th, 2014, 07:17 AM Go to last post
  3. Post FATAL ERROR while loading design "# Error loading design"

    Started by Rishi, March 20th, 2014 11:09 AM
    • Replies: 1
    • Views: 18,975
    March 24th, 2014, 07:13 AM Go to last post
  4. "gating" one process from another

    Started by richas, March 20th, 2014 09:49 AM
    • Replies: 1
    • Views: 17,583
    March 21st, 2014, 05:08 AM Go to last post
    • Replies: 1
    • Views: 17,527
    March 20th, 2014, 07:21 AM Go to last post
  5. Output bit stream

    Started by richas, March 19th, 2014 11:32 AM
    • Replies: 0
    • Views: 17,383
    March 19th, 2014, 11:32 AM Go to last post
  6. Read from sd card an image on DE2-115

    Started by anthimos, October 25th, 2013 03:21 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 34,266
    March 18th, 2014, 02:23 AM Go to last post
  7. tree structure

    Started by eva, February 24th, 2014 10:12 PM
    • Replies: 2
    • Views: 18,677
    March 16th, 2014, 04:08 AM Go to last post
  8. "VGA display" problem on DE2 board - Only 1 color on screen :(

    Started by bao09, December 29th, 2012 08:02 AM
    • Replies: 4
    • Views: 37,978
    March 14th, 2014, 05:25 PM Go to last post
  9. About logic and with bitwise and

    Started by buddha1987, March 13th, 2014 12:30 PM
    • Replies: 1
    • Views: 17,649
    March 13th, 2014, 11:37 PM Go to last post
  10. verlog code error

    Started by nisu, March 6th, 2014 08:16 PM
    • Replies: 2
    • Views: 17,848
    March 7th, 2014, 02:41 AM Go to last post
  11. Warning (15610): No output dependent on input pin

    Started by Abdulla873, February 26th, 2014 07:22 PM
    • Replies: 6
    • Views: 22,362
    February 28th, 2014, 01:28 PM Go to last post
  12. Signal related problem ----Stop the output (Urgent)

    Started by samsam0407, February 27th, 2014 01:41 AM
    • Replies: 4
    • Views: 17,694
    February 28th, 2014, 12:28 AM Go to last post
  13. Include file

    Started by Aflatoun, February 25th, 2014 12:44 PM
    • Replies: 1
    • Views: 17,745
    February 25th, 2014, 12:49 PM Go to last post
  14. SUm of table

    Started by Aflatoun, February 22nd, 2014 03:56 AM
    • Replies: 2
    • Views: 17,601
    February 25th, 2014, 12:41 PM Go to last post
  15. multiple constant drivers for net erro

    Started by Aflatoun, February 22nd, 2014 07:04 AM
    2 Pages
    1 2
    • Replies: 16
    • Views: 24,601
    February 23rd, 2014, 01:13 PM Go to last post
  16. Send Data to DE2 memory

    Started by danilojcamara, February 20th, 2014 12:02 PM
    de2, matlab, store data, verilog
    • Replies: 0
    • Views: 18,168
    February 20th, 2014, 12:02 PM Go to last post
  17. pwm generation

    Started by nisu, February 19th, 2014 04:32 AM
    • Replies: 5
    • Views: 20,423
    February 20th, 2014, 01:26 AM Go to last post
  18. pwm with varying frequency and clock

    Started by nisu, February 18th, 2014 08:07 PM
    • Replies: 1
    • Views: 18,510
    February 19th, 2014, 12:24 AM Go to last post
  19. Verilog syntax if statement

    Started by mhouse1, February 16th, 2014 01:12 PM
    else-if, syntax, verilog
    • Replies: 4
    • Views: 22,587
    February 16th, 2014, 09:38 PM Go to last post
  20. Unhappy pll based frequency synthesizer

    Started by nisu, February 11th, 2014 01:56 AM
    • Replies: 1
    • Views: 20,329
    February 15th, 2014, 08:08 AM Go to last post
  21. What's Wrong with This SV Code Involving Interfaces?

    Started by skrasms, February 13th, 2014 10:53 PM
    • Replies: 5
    • Views: 20,159
    February 14th, 2014, 03:05 PM Go to last post
  22. Problem with SV Interfaces in Quartus

    Started by skrasms, February 7th, 2014 09:30 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 22,428
    February 14th, 2014, 09:54 AM Go to last post
  23. Black Box

    Started by nepoch, February 13th, 2014 08:58 AM
    black box, encryption, pragma protect
    • Replies: 0
    • Views: 18,520
    February 13th, 2014, 08:58 AM Go to last post
  24. 16bit pwm register in fpga

    Started by nisu, February 6th, 2014 09:13 PM
    • Replies: 1
    • Views: 19,647
    February 7th, 2014, 02:56 AM Go to last post
  25. pwm verilog code

    Started by nisu, February 5th, 2014 03:06 AM
    • Replies: 7
    • Views: 22,318
    February 6th, 2014, 06:18 AM Go to last post
  26. error in verilog code

    Started by nisu, February 5th, 2014 01:03 AM
    • Replies: 4
    • Views: 18,988
    February 5th, 2014, 07:31 PM Go to last post
  27. Writing latches in verilog

    Started by starvsion, February 1st, 2014 02:07 PM
    • Replies: 1
    • Views: 18,171
    February 1st, 2014, 03:34 PM Go to last post
  28. IIR filter implementation in verilog

    Started by mz5, January 30th, 2014 10:48 PM
    iir filter in verilog
    • Replies: 2
    • Views: 21,267
    January 31st, 2014, 02:00 AM Go to last post
  29. clock division in verilog

    Started by danilojcamara, January 30th, 2014 04:46 AM
    clock division, de2
    • Replies: 2
    • Views: 18,233
    January 30th, 2014, 02:10 PM Go to last post

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