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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:48 PM
    • Replies: 0
    • Views: 43,557
    October 5th, 2012, 01:48 PM Go to last post
  1. pwm with varying frequency and clock

    Started by nisu, February 18th, 2014 08:07 PM
    • Replies: 1
    • Views: 18,364
    February 19th, 2014, 12:24 AM Go to last post
  2. Verilog syntax if statement

    Started by mhouse1, February 16th, 2014 01:12 PM
    else-if, syntax, verilog
    • Replies: 4
    • Views: 21,729
    February 16th, 2014, 09:38 PM Go to last post
  3. Unhappy pll based frequency synthesizer

    Started by nisu, February 11th, 2014 01:56 AM
    • Replies: 1
    • Views: 20,232
    February 15th, 2014, 08:08 AM Go to last post
  4. What's Wrong with This SV Code Involving Interfaces?

    Started by skrasms, February 13th, 2014 10:53 PM
    • Replies: 5
    • Views: 19,962
    February 14th, 2014, 03:05 PM Go to last post
  5. Problem with SV Interfaces in Quartus

    Started by skrasms, February 7th, 2014 09:30 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 22,195
    February 14th, 2014, 09:54 AM Go to last post
  6. Black Box

    Started by nepoch, February 13th, 2014 08:58 AM
    black box, encryption, pragma protect
    • Replies: 0
    • Views: 18,434
    February 13th, 2014, 08:58 AM Go to last post
  7. 16bit pwm register in fpga

    Started by nisu, February 6th, 2014 09:13 PM
    • Replies: 1
    • Views: 19,510
    February 7th, 2014, 02:56 AM Go to last post
  8. pwm verilog code

    Started by nisu, February 5th, 2014 03:06 AM
    • Replies: 7
    • Views: 21,956
    February 6th, 2014, 06:18 AM Go to last post
  9. error in verilog code

    Started by nisu, February 5th, 2014 01:03 AM
    • Replies: 4
    • Views: 18,831
    February 5th, 2014, 07:31 PM Go to last post
  10. Writing latches in verilog

    Started by starvsion, February 1st, 2014 02:07 PM
    • Replies: 1
    • Views: 17,999
    February 1st, 2014, 03:34 PM Go to last post
  11. IIR filter implementation in verilog

    Started by mz5, January 30th, 2014 10:48 PM
    iir filter in verilog
    • Replies: 2
    • Views: 21,092
    January 31st, 2014, 02:00 AM Go to last post
  12. clock division in verilog

    Started by danilojcamara, January 30th, 2014 04:46 AM
    clock division, de2
    • Replies: 2
    • Views: 18,063
    January 30th, 2014, 02:10 PM Go to last post
  13. Beginner question about making a beep sound

    Started by samsam0407, January 17th, 2014 10:49 AM
    • Replies: 3
    • Views: 18,889
    January 27th, 2014, 01:06 AM Go to last post
  14. Generate Shapes using Verilog

    Started by hubakboy, January 25th, 2014 06:28 AM
    • Replies: 0
    • Views: 18,768
    January 25th, 2014, 06:28 AM Go to last post
    • Replies: 3
    • Views: 20,054
    January 24th, 2014, 02:10 PM Go to last post
    • Replies: 0
    • Views: 17,785
    January 21st, 2014, 04:58 AM Go to last post
  15. Syntax to conditionally assign integer or parameter

    Started by frog1600, January 3rd, 2014 07:53 AM
    • Replies: 1
    • Views: 21,383
    January 3rd, 2014, 08:40 AM Go to last post
    • Replies: 2
    • Views: 20,951
    December 27th, 2013, 09:57 AM Go to last post
  16. Unhappy Help!! sound sensor with cyclone IV

    Started by mayarelmohr, December 24th, 2013 06:17 AM
    • Replies: 0
    • Views: 19,557
    December 24th, 2013, 06:17 AM Go to last post
  17. Basics - 2 inputs, 1 output + positive edges

    Started by piotr.kozierski, December 20th, 2013 03:56 AM
    • Replies: 2
    • Views: 21,220
    December 20th, 2013, 07:09 AM Go to last post
  18. Need Help - Object Tracking

    Started by phyrdows, December 20th, 2013 07:04 AM
    • Replies: 0
    • Views: 19,936
    December 20th, 2013, 07:04 AM Go to last post
  19. how to combine verilog module

    Started by Fauzan Ramli, December 19th, 2013 11:49 PM
    • Replies: 0
    • Views: 20,616
    December 19th, 2013, 11:49 PM Go to last post
  20. Question Line out port de1 .. help !

    Started by fahad_r89, November 30th, 2013 07:25 AM
    • Replies: 1
    • Views: 20,833
    December 10th, 2013, 04:59 PM Go to last post
    • Replies: 2
    • Views: 23,994
    December 10th, 2013, 07:40 AM Go to last post
  21. Question Module parameters

    Started by yuuul, December 2nd, 2013 03:46 PM
    module, parameters, verilog
    • Replies: 1
    • Views: 21,947
    December 4th, 2013, 01:39 AM Go to last post
  22. verilog code about shift phase 0, 90, 180, 270

    Started by sean98007, November 28th, 2013 07:56 AM
    • Replies: 6
    • Views: 26,036
    December 2nd, 2013, 02:42 PM Go to last post
    • Replies: 0
    • Views: 24,784
    November 27th, 2013, 03:13 PM Go to last post
  23. help creating delay in fsm

    Started by phaeight, November 25th, 2013 08:16 PM
    • Replies: 0
    • Views: 22,763
    November 25th, 2013, 08:16 PM Go to last post
  24. Help with verilog testbench code

    Started by defeduma, November 21st, 2013 02:18 AM
    • Replies: 1
    • Views: 22,562
    November 25th, 2013, 03:31 AM Go to last post
  25. verilog testbench file in emacs verilog mode

    Started by tba109, November 22nd, 2013 06:53 AM
    • Replies: 2
    • Views: 22,138
    November 22nd, 2013, 11:36 AM Go to last post

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