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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,818
    October 5th, 2012, 12:48 PM Go to last post
  1. verilog sdram_dll module

    Started by khama, February 22nd, 2013 10:36 AM
    • Replies: 0
    • Views: 31,321
    February 22nd, 2013, 10:36 AM Go to last post
  2. daft question about Verilog parameter

    Started by markaren1, February 21st, 2013 03:28 PM
    • Replies: 5
    • Views: 32,922
    February 21st, 2013, 06:03 PM Go to last post
  3. help with size optimization

    Started by markaren1, February 16th, 2013 06:29 AM
    • Replies: 0
    • Views: 31,702
    February 16th, 2013, 06:29 AM Go to last post
    • Replies: 2
    • Views: 40,755
    February 8th, 2013, 03:29 PM Go to last post
  4. Question Modelsim addition bug

    Started by lukvg, February 6th, 2013 06:25 PM
    adder, addition, bug, modelsim, verilog
    • Replies: 8
    • Views: 34,668
    February 6th, 2013, 11:45 PM Go to last post
  5. How to handle the no connection ports in a module?

    Started by buddha1987, February 5th, 2013 10:38 AM
    • Replies: 8
    • Views: 34,423
    February 6th, 2013, 11:23 AM Go to last post
  6. Assigning individual bits

    Started by Essentia, February 5th, 2013 12:36 PM
    • Replies: 4
    • Views: 30,297
    February 6th, 2013, 06:42 AM Go to last post
  7. simplest way to make a pin high or low in verilog

    Started by varunme, February 4th, 2013 11:25 PM
    • Replies: 1
    • Views: 32,275
    February 5th, 2013, 12:16 AM Go to last post
  8. Verilog code for bram

    Started by Jedstevens, January 9th, 2013 07:53 PM
    • Replies: 6
    • Views: 36,021
    February 1st, 2013, 12:15 PM Go to last post
  9. Any recommended tutorial for System Verilog?

    Started by buddha1987, January 25th, 2013 05:43 AM
    • Replies: 2
    • Views: 32,024
    January 29th, 2013, 06:02 PM Go to last post
  10. Simulation in quartus

    Started by dcheian, January 24th, 2013 05:22 PM
    • Replies: 1
    • Views: 30,124
    January 25th, 2013, 12:11 AM Go to last post
  11. CIC Filter: code not compiling!

    Started by hhachem, January 21st, 2013 11:33 AM
    filter, verilog
    • Replies: 4
    • Views: 35,780
    January 22nd, 2013, 10:13 AM Go to last post
  12. Strength

    Started by dcheian, January 21st, 2013 06:21 PM
    • Replies: 1
    • Views: 30,783
    January 22nd, 2013, 12:28 AM Go to last post
  13. Good technique for designing FSM

    Started by nervecell_23, January 17th, 2013 05:36 AM
    • Replies: 1
    • Views: 30,193
    January 17th, 2013, 07:09 AM Go to last post
  14. frequency to voltage converter

    Started by dcheian, January 15th, 2013 06:43 PM
    • Replies: 4
    • Views: 32,193
    January 16th, 2013, 11:22 AM Go to last post
  15. 20ns pulse generation at rising edge

    Started by phate, January 3rd, 2013 09:09 AM
    • Replies: 2
    • Views: 33,109
    January 11th, 2013, 11:56 AM Go to last post
  16. difference between `include and include

    Started by nervecell_23, January 11th, 2013 02:55 AM
    compile, include, verilog, warning
    • Replies: 1
    • Views: 33,042
    January 11th, 2013, 08:04 AM Go to last post
  17. 10.0c Modelsim Altera feature

    Started by bhanusinghal, December 29th, 2012 02:47 AM
    • Replies: 1
    • Views: 31,298
    January 11th, 2013, 07:34 AM Go to last post
  18. [Help] half band filter in verilog

    Started by trust0102, January 3rd, 2013 10:24 PM
    • Replies: 0
    • Views: 32,430
    January 3rd, 2013, 10:24 PM Go to last post
  19. SV fork/join and "run()" type functions, and SystemC

    Started by rpodosi, December 19th, 2012 07:03 AM
    systemc, systemverilog, threads
    • Replies: 0
    • Views: 31,467
    December 19th, 2012, 07:03 AM Go to last post
  20. Post Ports between blocks problem

    Started by almemar, December 18th, 2012 07:22 AM
    • Replies: 0
    • Views: 29,610
    December 18th, 2012, 07:22 AM Go to last post
  21. Help with this code

    Started by kh8402, December 17th, 2012 06:34 AM
    • Replies: 1
    • Views: 30,494
    December 18th, 2012, 01:13 AM Go to last post
    • Replies: 5
    • Views: 33,642
    December 13th, 2012, 09:57 AM Go to last post
  22. Can someone explain this?

    Started by dcheian, December 7th, 2012 11:26 AM
    • Replies: 3
    • Views: 31,423
    December 10th, 2012, 09:46 PM Go to last post
    • Replies: 2
    • Views: 34,030
    December 6th, 2012, 04:21 PM Go to last post
  23. HELP!!! Interfacing with ADC and FPGA board

    Started by brown2013, December 6th, 2012 10:39 AM
    • Replies: 0
    • Views: 34,077
    December 6th, 2012, 10:39 AM Go to last post
  24. De0 Nano ADC demo coding explanations

    Started by FunRunner, November 26th, 2012 06:09 PM
    • Replies: 2
    • Views: 34,204
    December 5th, 2012, 01:14 AM Go to last post
  25. LCD is always saying "Not Connected" !!!!

    Started by brown2013, November 29th, 2012 09:45 AM
    • Replies: 2
    • Views: 30,041
    December 2nd, 2012, 08:11 AM Go to last post
  26. Do I need synchronizer block for this

    Started by cpugeek, November 28th, 2012 12:43 PM
    siga
    • Replies: 6
    • Views: 34,032
    November 29th, 2012, 06:23 PM Go to last post
    • Replies: 1
    • Views: 33,209
    November 29th, 2012, 12:31 PM Go to last post

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