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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,271
    October 5th, 2012, 12:48 PM Go to last post
  1. CIC Filter: code not compiling!

    Started by hhachem, January 21st, 2013 11:33 AM
    filter, verilog
    • Replies: 4
    • Views: 35,441
    January 22nd, 2013, 10:13 AM Go to last post
  2. Strength

    Started by dcheian, January 21st, 2013 06:21 PM
    • Replies: 1
    • Views: 30,622
    January 22nd, 2013, 12:28 AM Go to last post
  3. Good technique for designing FSM

    Started by nervecell_23, January 17th, 2013 05:36 AM
    • Replies: 1
    • Views: 29,948
    January 17th, 2013, 07:09 AM Go to last post
  4. frequency to voltage converter

    Started by dcheian, January 15th, 2013 06:43 PM
    • Replies: 4
    • Views: 31,854
    January 16th, 2013, 11:22 AM Go to last post
  5. 20ns pulse generation at rising edge

    Started by phate, January 3rd, 2013 09:09 AM
    • Replies: 2
    • Views: 32,764
    January 11th, 2013, 11:56 AM Go to last post
  6. difference between `include and include

    Started by nervecell_23, January 11th, 2013 02:55 AM
    compile, include, verilog, warning
    • Replies: 1
    • Views: 32,724
    January 11th, 2013, 08:04 AM Go to last post
  7. 10.0c Modelsim Altera feature

    Started by bhanusinghal, December 29th, 2012 02:47 AM
    • Replies: 1
    • Views: 31,073
    January 11th, 2013, 07:34 AM Go to last post
  8. [Help] half band filter in verilog

    Started by trust0102, January 3rd, 2013 10:24 PM
    • Replies: 0
    • Views: 32,178
    January 3rd, 2013, 10:24 PM Go to last post
  9. SV fork/join and "run()" type functions, and SystemC

    Started by rpodosi, December 19th, 2012 07:03 AM
    systemc, systemverilog, threads
    • Replies: 0
    • Views: 31,199
    December 19th, 2012, 07:03 AM Go to last post
  10. Post Ports between blocks problem

    Started by almemar, December 18th, 2012 07:22 AM
    • Replies: 0
    • Views: 29,446
    December 18th, 2012, 07:22 AM Go to last post
  11. Help with this code

    Started by kh8402, December 17th, 2012 06:34 AM
    • Replies: 1
    • Views: 30,306
    December 18th, 2012, 01:13 AM Go to last post
    • Replies: 5
    • Views: 33,333
    December 13th, 2012, 09:57 AM Go to last post
  12. Can someone explain this?

    Started by dcheian, December 7th, 2012 11:26 AM
    • Replies: 3
    • Views: 31,179
    December 10th, 2012, 09:46 PM Go to last post
    • Replies: 2
    • Views: 33,666
    December 6th, 2012, 04:21 PM Go to last post
  13. HELP!!! Interfacing with ADC and FPGA board

    Started by brown2013, December 6th, 2012 10:39 AM
    • Replies: 0
    • Views: 33,864
    December 6th, 2012, 10:39 AM Go to last post
  14. De0 Nano ADC demo coding explanations

    Started by FunRunner, November 26th, 2012 06:09 PM
    • Replies: 2
    • Views: 33,932
    December 5th, 2012, 01:14 AM Go to last post
  15. LCD is always saying "Not Connected" !!!!

    Started by brown2013, November 29th, 2012 09:45 AM
    • Replies: 2
    • Views: 29,862
    December 2nd, 2012, 08:11 AM Go to last post
  16. Do I need synchronizer block for this

    Started by cpugeek, November 28th, 2012 12:43 PM
    siga
    • Replies: 6
    • Views: 33,703
    November 29th, 2012, 06:23 PM Go to last post
    • Replies: 1
    • Views: 32,969
    November 29th, 2012, 12:31 PM Go to last post
  17. reset using a counter doesn't work?

    Started by taliax, November 25th, 2012 11:35 PM
    • Replies: 1
    • Views: 31,601
    November 27th, 2012, 10:18 AM Go to last post
  18. signal delay

    Started by hujianhua, November 26th, 2012 10:22 PM
    • Replies: 0
    • Views: 29,162
    November 26th, 2012, 10:22 PM Go to last post
  19. Verilog always blocks

    Started by meetpatty, November 17th, 2012 05:26 PM
    • Replies: 4
    • Views: 33,012
    November 25th, 2012, 07:26 PM Go to last post
  20. Low Pass Frequency Filter in Verilog

    Started by dcheian, November 22nd, 2012 12:45 PM
    2 Pages
    1 2
    • Replies: 19
    • Views: 39,832
    November 25th, 2012, 02:15 PM Go to last post
  21. Smile verilog code

    Started by vivekkarthick, March 19th, 2012 12:25 AM
    • Replies: 5
    • Views: 41,068
    November 22nd, 2012, 12:41 PM Go to last post
  22. Smile verilog notes

    Started by vivekkarthick, March 19th, 2012 12:35 AM
    • Replies: 6
    • Views: 38,207
    November 22nd, 2012, 12:38 PM Go to last post
  23. FIFO holding one item in it

    Started by gygill, November 12th, 2012 10:06 AM
    • Replies: 2
    • Views: 29,985
    November 12th, 2012, 01:11 PM Go to last post
  24. Delay stimulus to be stored in scoreboard

    Started by jasonkee111, November 10th, 2012 05:00 AM
    • Replies: 0
    • Views: 28,448
    November 10th, 2012, 05:00 AM Go to last post
  25. counting from 1 to 9 every second

    Started by irishfan91, November 7th, 2012 03:37 PM
    • Replies: 1
    • Views: 30,334
    November 7th, 2012, 05:50 PM Go to last post
  26. Verilog parameter rounding

    Started by CosworthRS, November 3rd, 2012 04:15 AM
    • Replies: 1
    • Views: 31,640
    November 6th, 2012, 12:58 PM Go to last post
  27. nxn matrix inversion in verilog code

    Started by sffong2, October 30th, 2012 06:26 AM
    • Replies: 0
    • Views: 33,251
    October 30th, 2012, 06:26 AM Go to last post

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