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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:48 PM
    • Replies: 0
    • Views: 41,971
    October 5th, 2012, 01:48 PM Go to last post
  1. Question Curly braces

    Started by djp, August 11th, 2016 03:31 AM
    concatenation operator
    • Replies: 3
    • Views: 646
    August 11th, 2016, 09:45 PM Go to last post
    • Replies: 3
    • Views: 696
    August 3rd, 2016, 10:06 AM Go to last post
  2. Verilog code

    Started by gzbec040, July 22nd, 2016 11:18 PM
    • Replies: 1
    • Views: 590
    July 23rd, 2016, 03:26 AM Go to last post
  3. Implementing firmware version

    Started by Caliri, December 4th, 2012 02:28 AM
    3 Pages
    1 2 3
    • Replies: 22
    • Views: 33,985
    July 21st, 2016, 01:20 AM Go to last post
    • Replies: 4
    • Views: 914
    July 13th, 2016, 08:49 AM Go to last post
    • Replies: 13
    • Views: 1,316
    July 12th, 2016, 08:52 AM Go to last post
  4. Guidelines to avoid Negative Slack with State Machines

    Started by jeebujacob, June 29th, 2016 02:06 AM
    2 Pages
    1 2
    negative slack, setup violation, timing closure
    • Replies: 11
    • Views: 1,604
    July 10th, 2016, 09:32 PM Go to last post
  5. identifier error 10734

    Started by tolu, July 7th, 2016 12:04 PM
    • Replies: 1
    • Views: 509
    July 8th, 2016, 01:27 AM Go to last post
  6. Verilog Assignment

    Started by nanostallmann, July 6th, 2016 11:51 AM
    • Replies: 2
    • Views: 538
    July 6th, 2016, 01:36 PM Go to last post
  7. Module Instantiation Problem

    Started by faraz240, June 27th, 2016 09:05 PM
    • Replies: 2
    • Views: 915
    June 28th, 2016, 01:53 PM Go to last post
  8. Red face Difference between simulation and real test.

    Started by mrquan1506, June 19th, 2016 02:22 AM
    • Replies: 2
    • Views: 508
    June 22nd, 2016, 02:57 AM Go to last post
    • Replies: 4
    • Views: 855
    June 22nd, 2016, 02:43 AM Go to last post
  9. How to interface my verilog code with FFT ip core

    Started by mws000, June 15th, 2016 07:23 AM
    • Replies: 1
    • Views: 541
    June 20th, 2016, 06:45 AM Go to last post
  10. Post resistor capacitor

    Started by Chris7, June 6th, 2016 01:38 AM
    • Replies: 1
    • Views: 613
    June 7th, 2016, 05:34 AM Go to last post
  11. packages for synthesis

    Started by Shempington, June 2nd, 2016 11:14 AM
    package, synthesis, systemverilog
    • Replies: 1
    • Views: 516
    June 6th, 2016, 05:05 AM Go to last post
  12. Memory coding style

    Started by hdecharn, May 28th, 2016 03:07 AM
    • Replies: 5
    • Views: 681
    May 29th, 2016, 09:10 AM Go to last post
  13. Error 12007.

    Started by tolu, May 27th, 2016 02:56 PM
    • Replies: 1
    • Views: 491
    May 28th, 2016, 01:37 AM Go to last post
    • Replies: 3
    • Views: 544
    May 25th, 2016, 11:38 AM Go to last post
    • Replies: 0
    • Views: 417
    May 19th, 2016, 06:35 AM Go to last post
    • Replies: 0
    • Views: 421
    May 16th, 2016, 07:49 PM Go to last post
    • Replies: 4
    • Views: 952
    May 16th, 2016, 10:05 AM Go to last post
  14. verilog code for pid controller

    Started by pamasapr, May 9th, 2016 11:53 PM
    • Replies: 1
    • Views: 617
    May 10th, 2016, 04:23 AM Go to last post
  15. Using RAM for register

    Started by baev_al, March 27th, 2016 11:14 AM
    • Replies: 4
    • Views: 786
    May 9th, 2016, 12:18 PM Go to last post
    • Replies: 1
    • Views: 800
    May 9th, 2016, 12:14 PM Go to last post
  16. Automated Verilog Module Instantiation

    Started by sauhaarda, April 25th, 2016 08:44 PM
    • Replies: 1
    • Views: 491
    April 25th, 2016, 09:48 PM Go to last post
  17. Add subtract seven segments display

    Started by rkstm, April 17th, 2016 01:37 PM
    7 segment, display, mux, seven segment, verilog
    • Replies: 1
    • Views: 606
    April 18th, 2016, 12:06 AM Go to last post
  18. Multiple state machines in one module

    Started by RobEE, February 16th, 2016 06:06 PM
    • Replies: 2
    • Views: 809
    April 16th, 2016, 09:03 AM Go to last post
  19. Verilog Question with Quartus.

    Started by btaylor, April 15th, 2016 07:28 AM
    • Replies: 5
    • Views: 731
    April 15th, 2016, 02:12 PM Go to last post
  20. Mapping inout to inout

    Started by sveinse, April 12th, 2016 06:40 AM
    • Replies: 3
    • Views: 649
    April 12th, 2016, 12:21 PM Go to last post
  21. Cool "+" operation with odd number

    Started by junqiyang, April 11th, 2016 08:10 AM
    +;verilog
    • Replies: 2
    • Views: 507
    April 12th, 2016, 01:06 AM Go to last post

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