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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,811
    October 5th, 2012, 12:48 PM Go to last post
  1. Question How to generate Global RESET signal in Verilog?

    Started by knowfish, August 12th, 2016 01:42 AM
    2 Pages
    1 2
    asynchronous reset, fpga reset, reset signal generation, synchronous reset
    • Replies: 11
    • Views: 3,454
    January 4th, 2017, 04:17 AM Go to last post
  2. basic always block question

    Started by Numinus1, January 2nd, 2017 12:09 AM
    • Replies: 1
    • Views: 907
    January 2nd, 2017, 01:18 AM Go to last post
  3. MegaWizard 2x8k Dual Port Memory

    Started by HarryPothead, November 19th, 2016 07:01 AM
    • Replies: 4
    • Views: 1,430
    November 26th, 2016, 05:14 AM Go to last post
    • Replies: 0
    • Views: 918
    November 8th, 2016, 02:09 PM Go to last post
  4. Pseudo Random Bit Sequence Verilog

    Started by SumeetB, October 5th, 2016 01:56 PM
    bit sequence, spf+, stratix v, verilog
    • Replies: 3
    • Views: 1,507
    November 7th, 2016, 09:11 AM Go to last post
  5. TSW1400EVM / Altera Stratix IV / PLL replacement

    Started by ZEZE, July 20th, 2016 02:30 AM
    altera stratix iv, pll replacement, tsw1400evm
    • Replies: 5
    • Views: 1,728
    November 6th, 2016, 09:19 PM Go to last post
  6. DE2-70 Stereo vision

    Started by TSchokker, May 26th, 2016 03:33 AM
    camera, de2-70, disparity, disparity map, stereo vision
    • Replies: 1
    • Views: 1,255
    November 3rd, 2016, 06:42 AM Go to last post
    • Replies: 3
    • Views: 1,176
    October 31st, 2016, 02:28 PM Go to last post
    • Replies: 3
    • Views: 1,174
    October 31st, 2016, 06:25 AM Go to last post
  7. Red face The numbers stored in memory in verilog

    Started by faramarzsy, October 13th, 2016 11:25 PM
    • Replies: 0
    • Views: 888
    October 13th, 2016, 11:25 PM Go to last post
  8. reg [ x +: 12] mean ?

    Started by kavinda, October 6th, 2016 01:07 AM
    • Replies: 2
    • Views: 1,056
    October 6th, 2016, 07:31 AM Go to last post
  9. Array Elements and Indexing

    Started by kavinda, October 5th, 2016 05:13 PM
    • Replies: 2
    • Views: 1,067
    October 5th, 2016, 11:29 PM Go to last post
  10. Assigning pins in DE2 115

    Started by varunme, March 26th, 2013 11:13 PM
    • Replies: 8
    • Views: 35,852
    October 4th, 2016, 11:36 PM Go to last post
    • Replies: 5
    • Views: 1,769
    October 4th, 2016, 03:50 AM Go to last post
  11. Quartus reports:can't pass value from actual to argument xxx.

    Started by Mr.John, September 27th, 2016 12:45 AM
    systemverilog
    • Replies: 3
    • Views: 1,193
    September 30th, 2016, 01:21 AM Go to last post
  12. Quartus reports:can't pass value from actual to argument xxx.

    Started by Mr.John, September 27th, 2016 12:39 AM
    systemverilog
    • Replies: 0
    • Views: 614
    September 27th, 2016, 12:39 AM Go to last post
  13. verilog code for distributed arithemetic.

    Started by sathia, March 1st, 2014 05:45 AM
    • Replies: 7
    • Views: 19,441
    September 20th, 2016, 01:41 AM Go to last post
  14. verilog task passing values

    Started by stuck@sv, September 18th, 2016 06:20 AM
    task, verilog
    • Replies: 7
    • Views: 1,325
    September 19th, 2016, 06:31 AM Go to last post
  15. How to use a module or interface instance in an interface?

    Started by Mr.John, August 31st, 2016 06:40 PM
    2 Pages
    1 2
    interface, systemverilog
    • Replies: 11
    • Views: 1,993
    September 8th, 2016, 07:41 PM Go to last post
    • Replies: 1
    • Views: 849
    September 7th, 2016, 01:12 PM Go to last post
    • Replies: 1
    • Views: 1,063
    September 7th, 2016, 12:47 PM Go to last post
  16. inout wire logic, quartus15.1, error

    Started by putnik47, July 28th, 2016 08:04 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 2,147
    September 7th, 2016, 12:37 AM Go to last post
  17. Checking the RAM and Inserting Image into in a RAM

    Started by man1has, August 25th, 2016 02:52 AM
    • Replies: 2
    • Views: 864
    August 25th, 2016, 08:16 PM Go to last post
  18. Question 10 tap fir filter in verilog

    Started by soorajs, August 24th, 2016 02:21 AM
    • Replies: 5
    • Views: 1,124
    August 25th, 2016, 03:43 PM Go to last post
  19. Counter, synthesize problems

    Started by adacho94, August 19th, 2016 10:47 AM
    • Replies: 1
    • Views: 1,037
    August 22nd, 2016, 02:50 AM Go to last post
  20. Lightbulb Request of feedback on SPI Slave moduel

    Started by zehortigoza, August 18th, 2016 02:07 PM
    max10, slave, spi
    • Replies: 2
    • Views: 958
    August 19th, 2016, 06:11 AM Go to last post
    • Replies: 10
    • Views: 2,163
    August 15th, 2016, 04:32 AM Go to last post
  21. Question Curly braces

    Started by djp, August 11th, 2016 02:31 AM
    concatenation operator
    • Replies: 3
    • Views: 1,186
    August 11th, 2016, 08:45 PM Go to last post
    • Replies: 3
    • Views: 1,258
    August 3rd, 2016, 09:06 AM Go to last post
  22. Verilog code

    Started by gzbec040, July 22nd, 2016 10:18 PM
    • Replies: 1
    • Views: 1,015
    July 23rd, 2016, 02:26 AM Go to last post

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