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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 44,518
    October 5th, 2012, 12:48 PM Go to last post
    • Replies: 5
    • Views: 1,316
    December 1st, 2017, 09:05 AM Go to last post
  1. Understanding SHA 256 verilog design

    Started by newbiverification, November 30th, 2017 07:11 AM
    #sha, #sha256, #systemverilog, #verilog
    • Replies: 0
    • Views: 869
    November 30th, 2017, 07:11 AM Go to last post
    • Replies: 2
    • Views: 991
    November 29th, 2017, 01:52 PM Go to last post
  2. Code conversion

    Started by incmrh, November 28th, 2017 10:56 AM
    and systemverilog, verilog
    • Replies: 7
    • Views: 1,391
    November 29th, 2017, 04:12 AM Go to last post
  3. No control Nested If condition ?

    Started by esso1972, November 23rd, 2017 10:12 PM
    • Replies: 2
    • Views: 1,022
    November 23rd, 2017, 11:52 PM Go to last post
  4. MvcHome

    Started by rod@ariradesign.com, July 31st, 2017 11:19 AM
    • Replies: 1
    • Views: 1,423
    November 22nd, 2017, 09:07 PM Go to last post
  5. FSM miley machine

    Started by Verilogoz, November 14th, 2017 01:50 AM
    • Replies: 6
    • Views: 1,675
    November 22nd, 2017, 08:55 PM Go to last post
  6. set design clock

    Started by cicga, November 21st, 2017 06:26 AM
    • Replies: 5
    • Views: 1,357
    November 22nd, 2017, 05:37 AM Go to last post
  7. Creating square waves of varying frequencies

    Started by gSide, November 16th, 2017 12:35 PM
    audio, audio core, verilog
    • Replies: 2
    • Views: 1,067
    November 17th, 2017, 10:06 AM Go to last post
  8. hdmi cyclone 2...

    Started by solidcore, November 7th, 2017 03:27 PM
    • Replies: 8
    • Views: 2,153
    November 14th, 2017, 08:49 AM Go to last post
  9. DDR2_SDRAM Interface to Cyclone-3 device

    Started by jayakrushna, June 16th, 2017 05:21 AM
    • Replies: 2
    • Views: 2,254
    October 29th, 2017, 10:51 PM Go to last post
  10. Creating my own interface standard

    Started by Camper, October 24th, 2017 08:48 AM
    • Replies: 3
    • Views: 1,202
    October 29th, 2017, 05:43 AM Go to last post
  11. Question system verilog

    Started by harinathdigital@gmail.com, October 18th, 2017 04:21 PM
    • Replies: 1
    • Views: 1,025
    October 18th, 2017, 09:35 PM Go to last post
  12. Request for a verification code example in Verilog

    Started by bit_an, October 18th, 2017 07:34 AM
    programing, testbench, verification, verilog
    • Replies: 0
    • Views: 770
    October 18th, 2017, 07:34 AM Go to last post
  13. Verilog coding

    Started by cicga, October 5th, 2017 05:46 AM
    • Replies: 4
    • Views: 1,537
    October 6th, 2017, 06:24 AM Go to last post
  14. FSM: a state gets latched

    Started by dman, July 7th, 2017 05:39 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 4,456
    September 24th, 2017, 02:19 AM Go to last post
  15. Basic Verilog Codes for DE0 board

    Started by naresh_ank, September 6th, 2017 12:29 PM
    • Replies: 2
    • Views: 1,638
    September 6th, 2017, 02:45 PM Go to last post
  16. Need help capturing the period of a wave form. (Verilog)

    Started by Metaeyo, August 2nd, 2017 07:59 PM
    • Replies: 3
    • Views: 2,220
    August 14th, 2017, 03:27 PM Go to last post
  17. Question Cannot run stimulus module using Quartus Prime?

    Started by nbstrong, April 22nd, 2017 01:58 PM
    • Replies: 4
    • Views: 3,185
    August 5th, 2017, 09:10 PM Go to last post
  18. Testbench Events in ModelSim-Altera Starter Edition

    Started by joe306, August 2nd, 2017 05:54 AM
    • Replies: 3
    • Views: 1,341
    August 2nd, 2017, 03:07 PM Go to last post
    • Replies: 0
    • Views: 1,382
    July 26th, 2017, 02:53 PM Go to last post
    • Replies: 4
    • Views: 2,163
    July 24th, 2017, 09:05 AM Go to last post
  19. Help with Verilog structure

    Started by deanc, July 11th, 2017 07:00 AM
    • Replies: 2
    • Views: 1,562
    July 11th, 2017, 07:36 AM Go to last post
  20. Sequence of operations

    Started by iulianvalentin, July 9th, 2017 12:21 AM
    • Replies: 2
    • Views: 1,466
    July 9th, 2017, 09:21 PM Go to last post
  21. $readmemh() reference error

    Started by abdul aziz, July 9th, 2017 06:19 PM
    • Replies: 0
    • Views: 1,062
    July 9th, 2017, 06:19 PM Go to last post
  22. Assigning pins in DE2 115

    Started by varunme, March 26th, 2013 11:13 PM
    • Replies: 9
    • Views: 40,196
    July 3rd, 2017, 10:35 AM Go to last post
  23. Writing Fast State Machines using SystemVerilog

    Started by joe306, June 28th, 2017 08:34 AM
    • Replies: 3
    • Views: 1,810
    June 28th, 2017, 11:26 AM Go to last post
  24. Verilog: multiple conditions inside an if statement

    Started by dman, June 24th, 2017 05:37 AM
    • Replies: 1
    • Views: 1,760
    June 24th, 2017, 12:13 PM Go to last post
  25. Latches in frequecny divider using fsm implementation

    Started by avben, June 7th, 2017 12:38 PM
    2 Pages
    1 2
    • Replies: 19
    • Views: 4,949
    June 11th, 2017, 12:01 AM Go to last post
  26. degedge count problem..

    Started by ibrahimerbas, June 10th, 2017 05:56 AM
    • Replies: 1
    • Views: 1,121
    June 10th, 2017, 09:53 AM Go to last post

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