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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 42,810
    October 5th, 2012, 12:48 PM Go to last post
  1. Implementing firmware version

    Started by Caliri, December 4th, 2012 01:28 AM
    3 Pages
    1 2 3
    • Replies: 22
    • Views: 35,292
    July 21st, 2016, 12:20 AM Go to last post
    • Replies: 4
    • Views: 1,459
    July 13th, 2016, 07:49 AM Go to last post
    • Replies: 13
    • Views: 2,419
    July 12th, 2016, 07:52 AM Go to last post
  2. Guidelines to avoid Negative Slack with State Machines

    Started by jeebujacob, June 29th, 2016 01:06 AM
    2 Pages
    1 2
    negative slack, setup violation, timing closure
    • Replies: 11
    • Views: 2,400
    July 10th, 2016, 08:32 PM Go to last post
  3. identifier error 10734

    Started by tolu, July 7th, 2016 11:04 AM
    • Replies: 1
    • Views: 890
    July 8th, 2016, 12:27 AM Go to last post
  4. Verilog Assignment

    Started by nanostallmann, July 6th, 2016 10:51 AM
    • Replies: 2
    • Views: 962
    July 6th, 2016, 12:36 PM Go to last post
  5. Module Instantiation Problem

    Started by faraz240, June 27th, 2016 08:05 PM
    • Replies: 2
    • Views: 2,044
    June 28th, 2016, 12:53 PM Go to last post
  6. Red face Difference between simulation and real test.

    Started by mrquan1506, June 19th, 2016 01:22 AM
    • Replies: 2
    • Views: 938
    June 22nd, 2016, 01:57 AM Go to last post
    • Replies: 4
    • Views: 1,412
    June 22nd, 2016, 01:43 AM Go to last post
  7. How to interface my verilog code with FFT ip core

    Started by mws000, June 15th, 2016 06:23 AM
    • Replies: 1
    • Views: 997
    June 20th, 2016, 05:45 AM Go to last post
  8. Post resistor capacitor

    Started by Chris7, June 6th, 2016 12:38 AM
    • Replies: 1
    • Views: 1,007
    June 7th, 2016, 04:34 AM Go to last post
  9. packages for synthesis

    Started by Shempington, June 2nd, 2016 10:14 AM
    package, synthesis, systemverilog
    • Replies: 1
    • Views: 885
    June 6th, 2016, 04:05 AM Go to last post
  10. Memory coding style

    Started by hdecharn, May 28th, 2016 02:07 AM
    • Replies: 5
    • Views: 1,108
    May 29th, 2016, 08:10 AM Go to last post
  11. Error 12007.

    Started by tolu, May 27th, 2016 01:56 PM
    • Replies: 1
    • Views: 995
    May 28th, 2016, 12:37 AM Go to last post
    • Replies: 3
    • Views: 933
    May 25th, 2016, 10:38 AM Go to last post
    • Replies: 0
    • Views: 793
    May 19th, 2016, 05:35 AM Go to last post
    • Replies: 4
    • Views: 1,663
    May 16th, 2016, 09:05 AM Go to last post
  12. verilog code for pid controller

    Started by pamasapr, May 9th, 2016 10:53 PM
    • Replies: 1
    • Views: 1,184
    May 10th, 2016, 03:23 AM Go to last post
  13. Using RAM for register

    Started by baev_al, March 27th, 2016 10:14 AM
    • Replies: 4
    • Views: 1,193
    May 9th, 2016, 11:18 AM Go to last post
    • Replies: 1
    • Views: 1,390
    May 9th, 2016, 11:14 AM Go to last post
  14. Automated Verilog Module Instantiation

    Started by sauhaarda, April 25th, 2016 07:44 PM
    • Replies: 1
    • Views: 871
    April 25th, 2016, 08:48 PM Go to last post
  15. Add subtract seven segments display

    Started by rkstm, April 17th, 2016 12:37 PM
    7 segment, display, mux, seven segment, verilog
    • Replies: 1
    • Views: 1,055
    April 17th, 2016, 11:06 PM Go to last post
  16. Multiple state machines in one module

    Started by RobEE, February 16th, 2016 05:06 PM
    • Replies: 2
    • Views: 1,369
    April 16th, 2016, 08:03 AM Go to last post
  17. Verilog Question with Quartus.

    Started by btaylor, April 15th, 2016 06:28 AM
    • Replies: 5
    • Views: 1,162
    April 15th, 2016, 01:12 PM Go to last post
  18. Mapping inout to inout

    Started by sveinse, April 12th, 2016 05:40 AM
    • Replies: 3
    • Views: 1,040
    April 12th, 2016, 11:21 AM Go to last post
  19. Cool "+" operation with odd number

    Started by junqiyang, April 11th, 2016 07:10 AM
    +;verilog
    • Replies: 2
    • Views: 883
    April 12th, 2016, 12:06 AM Go to last post
  20. How to call a module from an always block?

    Started by Arvindmeti2710, April 4th, 2016 09:17 AM
    • Replies: 2
    • Views: 1,007
    April 4th, 2016, 09:37 AM Go to last post
  21. Question UART received data getting corrupted

    Started by vish2648, April 3rd, 2016 10:46 PM
    • Replies: 0
    • Views: 804
    April 3rd, 2016, 10:46 PM Go to last post
  22. ADC 0804 in FPGA DE2-70

    Started by suhaibalises, April 3rd, 2016 01:18 AM
    • Replies: 0
    • Views: 831
    April 3rd, 2016, 01:18 AM Go to last post
  23. Array indexing questions

    Started by qingcong, March 30th, 2016 10:49 AM
    • Replies: 3
    • Views: 1,082
    March 30th, 2016, 01:42 PM Go to last post

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