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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:48 PM
    • Replies: 0
    • Views: 42,054
    October 5th, 2012, 01:48 PM Go to last post
  1. Add subtract seven segments display

    Started by rkstm, April 17th, 2016 01:37 PM
    7 segment, display, mux, seven segment, verilog
    • Replies: 1
    • Views: 667
    April 18th, 2016, 12:06 AM Go to last post
  2. Multiple state machines in one module

    Started by RobEE, February 16th, 2016 06:06 PM
    • Replies: 2
    • Views: 895
    April 16th, 2016, 09:03 AM Go to last post
  3. Verilog Question with Quartus.

    Started by btaylor, April 15th, 2016 07:28 AM
    • Replies: 5
    • Views: 825
    April 15th, 2016, 02:12 PM Go to last post
  4. Mapping inout to inout

    Started by sveinse, April 12th, 2016 06:40 AM
    • Replies: 3
    • Views: 709
    April 12th, 2016, 12:21 PM Go to last post
  5. Cool "+" operation with odd number

    Started by junqiyang, April 11th, 2016 08:10 AM
    +;verilog
    • Replies: 2
    • Views: 560
    April 12th, 2016, 01:06 AM Go to last post
  6. How to call a module from an always block?

    Started by Arvindmeti2710, April 4th, 2016 10:17 AM
    • Replies: 2
    • Views: 623
    April 4th, 2016, 10:37 AM Go to last post
  7. Question UART received data getting corrupted

    Started by vish2648, April 3rd, 2016 11:46 PM
    • Replies: 0
    • Views: 535
    April 3rd, 2016, 11:46 PM Go to last post
  8. ADC 0804 in FPGA DE2-70

    Started by suhaibalises, April 3rd, 2016 02:18 AM
    • Replies: 0
    • Views: 568
    April 3rd, 2016, 02:18 AM Go to last post
  9. Array indexing questions

    Started by qingcong, March 30th, 2016 11:49 AM
    • Replies: 3
    • Views: 762
    March 30th, 2016, 02:42 PM Go to last post
  10. Unsupported feature error

    Started by loumbut5, March 29th, 2016 10:59 PM
    passgate, primitives, verilog
    • Replies: 1
    • Views: 682
    March 30th, 2016, 12:11 AM Go to last post
  11. example verilog code for connecting camera module ?

    Started by dkfxpfk, March 28th, 2016 06:26 AM
    • Replies: 1
    • Views: 696
    March 29th, 2016, 08:26 AM Go to last post
  12. Verilog/ VHDL code for bloom filter

    Started by swatz, March 28th, 2016 03:53 PM
    • Replies: 0
    • Views: 632
    March 28th, 2016, 03:53 PM Go to last post
  13. A synchronous clear enable conter RTL

    Started by bqwer, March 23rd, 2016 01:43 AM
    counter, rtl, template
    • Replies: 0
    • Views: 494
    March 23rd, 2016, 01:43 AM Go to last post
  14. Question Creating Video Output

    Started by Migsi, March 22nd, 2016 08:03 AM
    • Replies: 0
    • Views: 505
    March 22nd, 2016, 08:03 AM Go to last post
  15. Problem with Qsys when creating PIO

    Started by don3t, April 11th, 2013 07:31 AM
    • Replies: 3
    • Views: 31,834
    March 11th, 2016, 03:00 PM Go to last post
  16. 74LS190 Verilog Code

    Started by nizdom, February 21st, 2016 12:13 AM
    74ls190, counter, up/down counter, verilog
    • Replies: 1
    • Views: 823
    March 1st, 2016, 02:25 AM Go to last post
  17. FPGA Beginner Question

    Started by elenacoso, February 24th, 2016 10:18 AM
    • Replies: 1
    • Views: 669
    February 24th, 2016, 10:59 AM Go to last post
  18. ADC0804 verilog code interface to DE2 115 cyclone 4

    Started by zar, February 18th, 2016 08:38 AM
    • Replies: 1
    • Views: 775
    February 22nd, 2016, 03:01 AM Go to last post
    • Replies: 0
    • Views: 547
    February 16th, 2016, 10:28 PM Go to last post
    • Replies: 15
    • Views: 3,053
    February 13th, 2016, 03:16 AM Go to last post
  19. Question UART Reciever not responding after reset

    Started by vish2648, February 11th, 2016 02:59 AM
    • Replies: 1
    • Views: 621
    February 12th, 2016, 03:10 AM Go to last post
  20. Post altera_sc_fifo problem - invalid first transfer

    Started by matey22, February 11th, 2016 11:37 AM
    • Replies: 5
    • Views: 1,019
    February 11th, 2016, 01:02 PM Go to last post
  21. altera_sc_fifo problem - invalid first transfer

    Started by matey22, February 11th, 2016 11:47 AM
    • Replies: 1
    • Views: 693
    February 11th, 2016, 11:53 AM Go to last post
  22. sine wave using Different duty cycles of PWM

    Started by sumityadav, November 17th, 2015 11:13 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 3,677
    February 10th, 2016, 07:07 AM Go to last post
  23. Post UART alternate data missing

    Started by vish2648, February 9th, 2016 02:55 AM
    • Replies: 2
    • Views: 651
    February 9th, 2016, 09:28 PM Go to last post
  24. config support for Quartus?

    Started by fpgabuilder, February 14th, 2014 01:18 AM
    ambiguous, config
    • Replies: 1
    • Views: 16,331
    January 30th, 2016, 05:37 PM Go to last post
  25. Question using configurations in ModelSim

    Started by felixipg, October 10th, 2013 05:51 AM
    • Replies: 1
    • Views: 30,828
    January 22nd, 2016, 11:50 AM Go to last post
  26. 8 bit counter veriloge code

    Started by Makram, January 10th, 2016 11:59 AM
    • Replies: 4
    • Views: 1,156
    January 19th, 2016, 06:04 PM Go to last post
  27. Question regarding pulse generation

    Started by cbarberis, January 15th, 2016 04:04 PM
    • Replies: 1
    • Views: 651
    January 18th, 2016, 06:06 AM Go to last post
  28. Help needed

    Started by avinashmenon, January 9th, 2016 05:17 PM
    12002, instantiation error, quartus ii
    • Replies: 1
    • Views: 715
    January 10th, 2016, 06:52 AM Go to last post

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