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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 44,796
    October 5th, 2012, 12:48 PM Go to last post
  1. flop-flop simulation in ModelSim

    Started by demsp, May 16th, 2018 09:55 PM
    • Replies: 6
    • Views: 363
    May 18th, 2018, 05:53 AM Go to last post
  2. SPI slave clock crossing domain?

    Started by JackBK, May 17th, 2018 08:25 PM
    • Replies: 0
    • Views: 87
    May 17th, 2018, 08:25 PM Go to last post
    • Replies: 6
    • Views: 513
    May 8th, 2018, 06:43 AM Go to last post
    • Replies: 7
    • Views: 806
    April 23rd, 2018, 10:07 PM Go to last post
    • Replies: 0
    • Views: 446
    April 11th, 2018, 06:34 AM Go to last post
  3. pi controller i verilog

    Started by kkp, March 23rd, 2018 01:21 PM
    • Replies: 1
    • Views: 404
    April 10th, 2018, 01:13 PM Go to last post
  4. Mixed blocking and non- with always@ ?

    Started by greglang, April 10th, 2018 03:05 AM
    • Replies: 4
    • Views: 428
    April 10th, 2018, 11:20 AM Go to last post
  5. Question delay a signal by several clk cycles in verilog

    Started by handaxiao, April 5th, 2018 04:28 PM
    • Replies: 1
    • Views: 372
    April 5th, 2018, 08:54 PM Go to last post
  6. Need help designing a Custom IP with Avalon Slave Interface

    Started by mh9840, March 31st, 2018 02:17 AM
    • Replies: 2
    • Views: 613
    March 31st, 2018, 12:08 PM Go to last post
  7. Strange code behavior, once it works, once not.

    Started by kgotfryd, March 30th, 2018 11:13 AM
    • Replies: 0
    • Views: 422
    March 30th, 2018, 11:13 AM Go to last post
  8. LED to clock in Register

    Started by demsp, March 17th, 2018 01:29 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 1,175
    March 25th, 2018, 08:56 AM Go to last post
  9. changing output from two always blocks

    Started by Bobdoe, March 20th, 2018 03:44 PM
    • Replies: 3
    • Views: 708
    March 22nd, 2018, 10:22 AM Go to last post
    • Replies: 0
    • Views: 454
    March 15th, 2018, 04:07 PM Go to last post
  10. adc_mic_lcd demonstration on NEEK max10

    Started by Djcx, March 14th, 2018 06:45 AM
    • Replies: 1
    • Views: 399
    March 15th, 2018, 06:04 AM Go to last post
  11. illegal inout port connections in vsim 3053

    Started by rainbow, March 14th, 2018 07:59 AM
    • Replies: 1
    • Views: 474
    March 14th, 2018, 09:54 AM Go to last post
  12. Parameter type not supported?

    Started by rgarciaf071, February 28th, 2018 07:55 AM
    • Replies: 5
    • Views: 1,171
    March 5th, 2018, 11:13 PM Go to last post
  13. task vs always

    Started by rock bog, March 3rd, 2018 12:41 PM
    • Replies: 4
    • Views: 728
    March 5th, 2018, 12:47 AM Go to last post
    • Replies: 0
    • Views: 450
    March 2nd, 2018, 01:47 PM Go to last post
  14. PI loop filter logic in Verilog

    Started by rock bog, February 23rd, 2018 07:19 AM
    • Replies: 3
    • Views: 925
    February 27th, 2018, 01:19 AM Go to last post
  15. How to use SCLR port of an Flip flop in Verilog?

    Started by zubeyr, February 21st, 2018 08:57 AM
    • Replies: 1
    • Views: 649
    February 22nd, 2018, 02:50 AM Go to last post
  16. Array Declaration cases

    Started by dmitryl, February 19th, 2018 10:34 AM
    • Replies: 2
    • Views: 596
    February 19th, 2018, 02:09 PM Go to last post
  17. Look Up Table of enum types -> declaration + usage -> how to?

    Started by dmitryl, February 19th, 2018 10:38 AM
    • Replies: 0
    • Views: 441
    February 19th, 2018, 10:38 AM Go to last post
  18. FIFO Works fine on EDAPlayground but not Quartus

    Started by ch701builder, February 16th, 2018 09:18 AM
    • Replies: 5
    • Views: 854
    February 16th, 2018, 04:29 PM Go to last post
  19. "j" is not a constant in verilog for loop addition

    Started by rozsatib, February 15th, 2018 08:48 AM
    • Replies: 3
    • Views: 752
    February 15th, 2018, 11:50 PM Go to last post
  20. Post Instantiate VHDL Generics with Verilog code (for testbench)

    Started by GGRANDA, February 8th, 2018 05:28 AM
    • Replies: 2
    • Views: 1,851
    February 8th, 2018, 06:16 AM Go to last post
  21. Convert AHDL to Verilog

    Started by DVDBE, October 10th, 2017 06:29 AM
    • Replies: 3
    • Views: 1,775
    January 29th, 2018, 09:04 AM Go to last post
  22. VGA and SDRAM verilog code.

    Started by 1610dinesh, January 21st, 2018 09:58 PM
    • Replies: 1
    • Views: 1,196
    January 22nd, 2018, 03:25 PM Go to last post
    • Replies: 7
    • Views: 1,704
    January 11th, 2018, 02:20 PM Go to last post
  23. Post Verilog coding help

    Started by saleem, January 1st, 2018 07:13 AM
    2 Pages
    1 2
    verilog coding
    • Replies: 11
    • Views: 2,072
    January 5th, 2018, 10:11 PM Go to last post
  24. Digital Alarm Clock

    Started by incmrh, December 10th, 2017 03:13 PM
    • Replies: 2
    • Views: 2,599
    December 27th, 2017, 09:11 PM Go to last post

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