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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:52 PM
    • Replies: 6
    • Views: 46,529
    October 28th, 2015, 01:36 PM Go to last post
  1. use verilog module in vhdl and the test bench

    Started by peteraobo, February 1st, 2016 07:44 AM
    • Replies: 5
    • Views: 1,442
    February 2nd, 2016, 01:35 AM Go to last post
  2. shift_left and shift_right for large vectors freeze Quartus

    Started by flz47655, January 27th, 2016 04:17 AM
    • Replies: 4
    • Views: 1,626
    January 27th, 2016, 06:34 AM Go to last post
  3. Adder with generic addend

    Started by nicx82, January 15th, 2016 03:19 AM
    • Replies: 1
    • Views: 909
    January 15th, 2016, 05:35 AM Go to last post
  4. Unhappy Error (10822) a code that dosent work

    Started by danieltkua, January 14th, 2016 09:59 PM
    • Replies: 1
    • Views: 937
    January 15th, 2016, 12:03 AM Go to last post
  5. vhdl real time clock

    Started by dzanab, January 12th, 2016 03:54 AM
    • Replies: 3
    • Views: 2,117
    January 14th, 2016, 09:22 AM Go to last post
  6. how to use clk in fsm

    Started by danieltkua, January 12th, 2016 09:44 AM
    • Replies: 1
    • Views: 1,032
    January 12th, 2016, 10:42 AM Go to last post
  7. how to get the main frequency from digital data

    Started by danieltkua, January 7th, 2016 05:01 AM
    • Replies: 1
    • Views: 1,077
    January 11th, 2016, 11:26 PM Go to last post
  8. Data from mif file

    Started by Bigbangbung, January 11th, 2016 05:43 AM
    • Replies: 1
    • Views: 1,016
    January 11th, 2016, 08:34 AM Go to last post
    • Replies: 2
    • Views: 1,534
    January 4th, 2016, 09:09 AM Go to last post
  9. Genrating vhdl code or vhdl file from java

    Started by sachinI1234, December 29th, 2015 05:47 AM
    • Replies: 5
    • Views: 2,701
    December 29th, 2015, 02:50 PM Go to last post
  10. converting java method to vhdl

    Started by Ms.Friday, May 18th, 2015 02:38 PM
    • Replies: 9
    • Views: 5,433
    December 29th, 2015, 06:09 AM Go to last post
  11. Post RISC 16 sequential implementation in vhdl

    Started by sanfoor, December 18th, 2015 02:03 PM
    vhdl
    • Replies: 2
    • Views: 2,587
    December 24th, 2015, 02:36 AM Go to last post
  12. Wink DE2: Audio Codec development - Walk with me please :)

    Started by MMalik, June 5th, 2014 03:01 AM
    audio codec, de2
    • Replies: 6
    • Views: 17,507
    December 24th, 2015, 01:38 AM Go to last post
  13. What it means ? 'left

    Started by aubinais, December 16th, 2015 10:37 PM
    • Replies: 2
    • Views: 2,699
    December 24th, 2015, 01:30 AM Go to last post
    • Replies: 5
    • Views: 2,394
    December 23rd, 2015, 02:22 PM Go to last post
  14. Mixed TDF/VHDL/BDF Project Files

    Started by jhooks, October 28th, 2015 05:25 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 5,378
    December 14th, 2015, 10:26 PM Go to last post
    • Replies: 5
    • Views: 3,370
    December 14th, 2015, 12:57 AM Go to last post
  15. Question about good design: overriding functions, function parameters or similar

    Started by alexK195, December 8th, 2015 07:40 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 3,366
    December 14th, 2015, 12:34 AM Go to last post
    • Replies: 7
    • Views: 3,886
    December 13th, 2015, 08:32 PM Go to last post
  16. Address generator using H_count and V_count on VGA

    Started by Minima, December 12th, 2015 09:12 AM
    • Replies: 1
    • Views: 2,075
    December 12th, 2015, 12:22 PM Go to last post
  17. Vhdl jpeg decoder

    Started by BurakB, December 7th, 2015 08:47 AM
    decoder, fpga, jpeg, vhdl
    • Replies: 6
    • Views: 5,318
    December 9th, 2015, 10:43 PM Go to last post
  18. Exclamation select a component generated by gernerate stsement

    Started by zips, December 9th, 2015 01:59 PM
    generate, select, vhdl
    • Replies: 1
    • Views: 2,678
    December 9th, 2015, 10:43 PM Go to last post
  19. Convert Matlab Code to VHDL small example

    Started by jam1988, December 9th, 2015 03:44 AM
    • Replies: 3
    • Views: 3,274
    December 9th, 2015, 11:08 AM Go to last post
  20. Clock gating with enable or not

    Started by sveinse, December 5th, 2015 03:15 PM
    • Replies: 5
    • Views: 3,271
    December 7th, 2015, 06:15 AM Go to last post
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  21. VGA controller help

    Started by amanarasa, December 5th, 2015 11:29 AM
    • Replies: 3
    • Views: 2,551
    December 6th, 2015, 06:39 PM Go to last post
  22. How to initialize a signal without any loops

    Started by MallocLee, December 5th, 2015 04:38 AM
    • Replies: 3
    • Views: 2,508
    December 5th, 2015, 09:27 AM Go to last post
  23. VHDL help

    Started by Gadda, December 3rd, 2015 10:53 AM
    • Replies: 1
    • Views: 2,371
    December 3rd, 2015, 02:07 PM Go to last post
  24. Inferred RAM: Pass-through logic generated despite no_rw_check

    Started by maikmaikmaik, December 2nd, 2015 10:29 AM
    2 Pages
    1 2
    attributes, ram inference, read-during-write, synthesis
    • Replies: 14
    • Views: 5,437
    December 3rd, 2015, 08:07 AM Go to last post
  25. How to access On Chip Memory in VHDL

    Started by crabtack, September 26th, 2015 06:49 AM
    • Replies: 3
    • Views: 4,767
    December 2nd, 2015, 09:39 PM Go to last post

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