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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:52 PM
    • Replies: 6
    • Views: 45,735
    October 28th, 2015, 12:36 PM Go to last post
  1. VGA controller help

    Started by amanarasa, December 5th, 2015 10:29 AM
    • Replies: 3
    • Views: 2,432
    December 6th, 2015, 05:39 PM Go to last post
  2. How to initialize a signal without any loops

    Started by MallocLee, December 5th, 2015 03:38 AM
    • Replies: 3
    • Views: 2,377
    December 5th, 2015, 08:27 AM Go to last post
  3. VHDL help

    Started by Gadda, December 3rd, 2015 09:53 AM
    • Replies: 1
    • Views: 2,283
    December 3rd, 2015, 01:07 PM Go to last post
  4. Inferred RAM: Pass-through logic generated despite no_rw_check

    Started by maikmaikmaik, December 2nd, 2015 09:29 AM
    2 Pages
    1 2
    attributes, ram inference, read-during-write, synthesis
    • Replies: 14
    • Views: 4,927
    December 3rd, 2015, 07:07 AM Go to last post
  5. How to access On Chip Memory in VHDL

    Started by crabtack, September 26th, 2015 05:49 AM
    • Replies: 3
    • Views: 4,555
    December 2nd, 2015, 08:39 PM Go to last post
  6. file read and write function fails to execute in functions

    Started by 747GO, November 30th, 2015 11:35 AM
    • Replies: 8
    • Views: 4,133
    December 1st, 2015, 07:02 PM Go to last post
  7. Concatenation in VHDL

    Started by Douglas Baldissera, November 28th, 2015 06:40 PM
    bits, concatenation, fpga, strings, vhdl
    • Replies: 7
    • Views: 4,257
    November 29th, 2015, 06:10 PM Go to last post
  8. Altera Cyclone 2 PLL

    Started by Skyline121212, November 24th, 2015 10:56 PM
    • Replies: 6
    • Views: 3,493
    November 27th, 2015, 03:00 AM Go to last post
  9. VGA monitor display

    Started by Minima, November 22nd, 2015 04:19 AM
    • Replies: 4
    • Views: 3,262
    November 24th, 2015, 09:17 AM Go to last post
  10. HiSpi protocol design example

    Started by bmw318, November 23rd, 2015 12:41 AM
    design example, hispi, vhdl
    • Replies: 0
    • Views: 2,743
    November 23rd, 2015, 12:41 AM Go to last post
  11. help me through vhdl code

    Started by SHAJITH, November 20th, 2015 03:41 AM
    • Replies: 3
    • Views: 2,975
    November 23rd, 2015, 12:21 AM Go to last post
  12. VHDL Code Help

    Started by Sandman, November 15th, 2015 04:01 PM
    • Replies: 3
    • Views: 3,026
    November 16th, 2015, 02:06 AM Go to last post
  13. Output from ROM

    Started by Minima, November 10th, 2015 05:09 AM
    • Replies: 4
    • Views: 3,033
    November 10th, 2015, 06:18 AM Go to last post
  14. DE2_Audio_Example VHDL project

    Started by SharpWeapon, November 6th, 2015 06:17 PM
    altera, audio codec, de2, verilog, vhdl
    • Replies: 1
    • Views: 3,768
    November 7th, 2015, 12:27 PM Go to last post
  15. Exclamation Error 10349 in test bench

    Started by CrayLeslie, November 6th, 2015 10:16 AM
    error 10349, vhdl
    • Replies: 2
    • Views: 2,966
    November 7th, 2015, 11:58 AM Go to last post
  16. Need advice about coding style

    Started by alex96, May 18th, 2015 09:42 AM
    4 Pages
    1 2 3 ... 4
    • Replies: 31
    • Views: 7,266
    November 6th, 2015, 10:17 AM Go to last post
  17. Content in ROM

    Started by Minima, November 4th, 2015 07:31 AM
    • Replies: 5
    • Views: 2,486
    November 5th, 2015, 12:34 AM Go to last post
  18. Thumbs up arithmetic mode for LE from vhdl

    Started by alex96, November 1st, 2015 03:32 AM
    arithmetic mode, vhdl
    • Replies: 8
    • Views: 3,765
    November 3rd, 2015, 09:39 AM Go to last post
  19. Missing Address in input node finder

    Started by Minima, November 2nd, 2015 03:51 AM
    • Replies: 1
    • Views: 1,985
    November 2nd, 2015, 04:44 AM Go to last post
  20. using multiple conversion statements

    Started by Skyline121212, October 31st, 2015 09:45 AM
    • Replies: 7
    • Views: 2,391
    October 31st, 2015, 11:58 AM Go to last post
  21. Question Assignments for vectors inequal in length

    Started by alex96, October 30th, 2015 02:34 PM
    • Replies: 5
    • Views: 2,303
    October 31st, 2015, 01:06 AM Go to last post
  22. Question The signal does not hold its value outside clock edge

    Started by decyfer12, October 17th, 2015 11:04 AM
    register, vhdl
    • Replies: 4
    • Views: 2,689
    October 30th, 2015, 04:42 AM Go to last post
  23. Code seems fine, can't find out where these errors are at. :(

    Started by ajm511, October 27th, 2015 02:39 PM
    • Replies: 5
    • Views: 3,379
    October 28th, 2015, 12:37 PM Go to last post
    • Replies: 8
    • Views: 3,733
    October 27th, 2015, 05:28 AM Go to last post
  24. Function in VHDL

    Started by Minima, October 24th, 2015 08:21 PM
    • Replies: 2
    • Views: 2,224
    October 25th, 2015, 01:31 AM Go to last post
    • Replies: 2
    • Views: 2,255
    October 21st, 2015, 06:45 PM Go to last post
  25. Exclamation Request for help in VHDL troubleshooting

    Started by Weichong, September 28th, 2015 06:01 AM
    3 Pages
    1 2 3
    • Replies: 20
    • Views: 5,325
    October 21st, 2015, 09:01 AM Go to last post
  26. Lightbulb attribute 'event usage within procedure

    Started by dipling, October 21st, 2015 02:18 AM
    • Replies: 5
    • Views: 2,310
    October 21st, 2015, 05:27 AM Go to last post
  27. Securely start a State-Machine with pulses or edges

    Started by Steffen.Doster, October 14th, 2015 02:01 AM
    3 Pages
    1 2 3
    • Replies: 20
    • Views: 4,978
    October 15th, 2015, 01:50 AM Go to last post
  28. Create multiple 'Cores' of my design

    Started by karthik.ganesan, October 12th, 2015 02:15 PM
    • Replies: 8
    • Views: 3,861
    October 14th, 2015, 05:09 AM Go to last post

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