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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:52 PM
    • Replies: 6
    • Views: 46,505
    October 28th, 2015, 01:36 PM Go to last post
  1. Customized signal

    Started by azrirhmn, May 18th, 2017 07:54 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 2,159
    May 19th, 2017, 11:31 AM Go to last post
  2. Testbench

    Started by orhan, May 16th, 2017 07:58 AM
    • Replies: 9
    • Views: 1,890
    May 19th, 2017, 06:36 AM Go to last post
  3. VHDL aggregate error

    Started by azrirhmn, May 19th, 2017 01:21 AM
    • Replies: 2
    • Views: 1,298
    May 19th, 2017, 01:43 AM Go to last post
  4. Replacing a process with 1-port RAM

    Started by NovNov, April 26th, 2017 05:55 PM
    3 Pages
    1 2 3
    • Replies: 21
    • Views: 4,787
    May 17th, 2017, 04:16 AM Go to last post
  5. Question Generic One-Hot Multiplexer

    Started by Aaron511, May 11th, 2017 02:25 PM
    • Replies: 4
    • Views: 2,336
    May 12th, 2017, 12:19 PM Go to last post
  6. not random at each execution

    Started by Sfato, May 9th, 2017 07:16 AM
    2 Pages
    1 2
    • Replies: 16
    • Views: 2,778
    May 11th, 2017, 01:08 PM Go to last post
  7. Register using component and port maps

    Started by ra23, May 9th, 2017 03:25 PM
    vhdl
    • Replies: 1
    • Views: 1,122
    May 9th, 2017, 10:59 PM Go to last post
  8. Synthesized away the following RAM node help

    Started by zhbai, May 5th, 2017 02:16 PM
    • Replies: 1
    • Views: 1,108
    May 5th, 2017, 11:38 PM Go to last post
  9. Strange comparator behavior

    Started by Pickwick, May 4th, 2017 01:25 PM
    • Replies: 2
    • Views: 1,081
    May 5th, 2017, 05:04 AM Go to last post
    • Replies: 2
    • Views: 1,339
    May 3rd, 2017, 07:51 AM Go to last post
  10. Problem reading RAM.

    Started by john7, April 30th, 2017 05:24 AM
    • Replies: 3
    • Views: 1,359
    April 30th, 2017, 11:00 PM Go to last post
  11. altera_attribute for regional_clock

    Started by jwiesemann, April 27th, 2017 01:54 AM
    altera_attribute, gloabl_signal, regional clock, syntax
    • Replies: 2
    • Views: 1,121
    April 28th, 2017, 05:43 PM Go to last post
  12. Asynchronous pulse generator code rising edge

    Started by jonhmiller, April 26th, 2017 03:59 PM
    • Replies: 8
    • Views: 2,305
    April 27th, 2017, 12:48 PM Go to last post
  13. VHDL Coding Help - Altera DE1 Board

    Started by sangamsaga, April 26th, 2017 05:05 PM
    • Replies: 1
    • Views: 1,067
    April 26th, 2017, 11:54 PM Go to last post
  14. ARRAY with a dynamic range

    Started by yossiwf, April 24th, 2017 06:34 AM
    • Replies: 3
    • Views: 1,392
    April 25th, 2017, 01:06 AM Go to last post
  15. variable initialization help

    Started by zhbai, April 22nd, 2017 02:41 PM
    • Replies: 9
    • Views: 2,230
    April 25th, 2017, 12:27 AM Go to last post
  16. Post RAM property help

    Started by zhbai, April 11th, 2017 03:28 PM
    • Replies: 7
    • Views: 1,925
    April 13th, 2017, 02:14 PM Go to last post
  17. Read in external ADC values

    Started by Christoph1990, April 8th, 2017 09:59 AM
    • Replies: 4
    • Views: 1,906
    April 11th, 2017, 09:46 PM Go to last post
  18. Question Clocking is too complex - error

    Started by Pickwick, April 8th, 2017 06:55 AM
    • Replies: 3
    • Views: 1,691
    April 8th, 2017, 03:19 PM Go to last post
  19. integer overflow

    Started by jreinauld, April 7th, 2017 06:43 AM
    • Replies: 2
    • Views: 1,389
    April 7th, 2017, 09:23 AM Go to last post
  20. Issues with access to array of accesses

    Started by jreinauld, April 5th, 2017 10:21 AM
    • Replies: 2
    • Views: 1,477
    April 6th, 2017, 01:01 AM Go to last post
  21. Parallel VHDL

    Started by FINCH1, March 26th, 2017 12:45 PM
    • Replies: 8
    • Views: 2,530
    April 4th, 2017, 01:33 AM Go to last post
  22. Multiple RAM with different mif file

    Started by zhbai, March 28th, 2017 09:39 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 3,026
    March 31st, 2017, 06:14 PM Go to last post
  23. Unhappy Error 10500 Help me !!!

    Started by milena199, March 28th, 2017 03:08 AM
    10500, error
    • Replies: 3
    • Views: 1,694
    March 30th, 2017, 10:46 PM Go to last post
    • Replies: 1
    • Views: 1,170
    March 28th, 2017, 03:00 AM Go to last post
  24. Post Synthesis simulation fails, problem with RTL?

    Started by tmny277, March 26th, 2017 08:14 PM
    • Replies: 3
    • Views: 1,629
    March 27th, 2017, 12:17 PM Go to last post
  25. Signal not assigned in init state

    Started by PuqmaStar, March 21st, 2017 09:20 PM
    2 Pages
    1 2
    • Replies: 16
    • Views: 3,726
    March 25th, 2017, 05:58 PM Go to last post
  26. VHDL "Quantum" bug

    Started by javieralso, March 17th, 2017 05:41 AM
    • Replies: 4
    • Views: 1,775
    March 21st, 2017, 08:07 AM Go to last post
  27. UART VDHL code not working getting only garbage values

    Started by G.Ornil, March 17th, 2017 02:26 AM
    de0-nani-soc, fpga cyclone v, uart, vhdl
    • Replies: 1
    • Views: 1,392
    March 20th, 2017, 02:08 PM Go to last post
  28. Edge detection asynchronous signal fails

    Started by PuqmaStar, March 18th, 2017 07:15 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 3,122
    March 20th, 2017, 01:12 AM Go to last post

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