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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:52 PM
    • Replies: 6
    • Views: 44,100
    October 28th, 2015, 12:36 PM Go to last post
  1. File not simulating with ModelSim-Altera

    Started by Hozan677, January 11th, 2017 10:32 AM
    • Replies: 5
    • Views: 585
    January 16th, 2017, 06:41 AM Go to last post
  2. Dual Clock FIFO Implementation VHDL

    Started by abrownlie, January 9th, 2017 06:55 AM
    • Replies: 4
    • Views: 748
    January 15th, 2017, 11:49 PM Go to last post
  3. Shift constant by variable amount

    Started by sstrell, January 14th, 2017 08:07 AM
    • Replies: 2
    • Views: 365
    January 14th, 2017, 02:45 PM Go to last post
  4. Can't Simulate Buffer port in ModelSim

    Started by Hozan677, January 9th, 2017 07:35 AM
    • Replies: 2
    • Views: 369
    January 9th, 2017, 08:00 AM Go to last post
  5. MIDI Manager

    Started by FPGApadawan, January 7th, 2017 11:54 AM
    • Replies: 2
    • Views: 403
    January 8th, 2017, 05:04 AM Go to last post
  6. Websites providing professional help

    Started by Hozan677, January 4th, 2017 11:02 AM
    • Replies: 5
    • Views: 620
    January 7th, 2017, 05:34 PM Go to last post
  7. Frequency division for use in an 8x1 multiplexer

    Started by Hozan677, December 24th, 2016 06:44 AM
    • Replies: 3
    • Views: 491
    January 1st, 2017, 09:16 AM Go to last post
  8. UART issue

    Started by FPGApadawan, December 29th, 2016 10:08 AM
    • Replies: 5
    • Views: 619
    December 30th, 2016, 12:31 PM Go to last post
  9. using lpm_counter to divide a clock by any No

    Started by Hozan677, December 22nd, 2016 08:21 AM
    • Replies: 4
    • Views: 583
    December 29th, 2016, 06:53 AM Go to last post
  10. Question about True Dual Port RAM

    Started by snouppie, December 18th, 2016 02:52 AM
    • Replies: 6
    • Views: 783
    December 23rd, 2016, 12:33 PM Go to last post
  11. How to use a for loop for repetitive timed actions

    Started by mafstoffer, December 16th, 2016 02:08 PM
    • Replies: 6
    • Views: 765
    December 19th, 2016, 02:23 PM Go to last post
  12. One port ram question

    Started by zhbai, December 17th, 2016 12:42 PM
    on chip memory, one port memory, vhdl
    • Replies: 3
    • Views: 540
    December 19th, 2016, 01:25 PM Go to last post
  13. How to avoid delay

    Started by snouppie, December 14th, 2016 03:06 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 1,064
    December 16th, 2016, 11:11 AM Go to last post
  14. Simulation of Block Diagram Schematics Project

    Started by Hozan677, December 15th, 2016 05:45 AM
    • Replies: 1
    • Views: 389
    December 15th, 2016, 10:12 AM Go to last post
  15. Simulation Report NOT RESPONDING

    Started by djh36, September 29th, 2016 09:10 AM
    • Replies: 8
    • Views: 1,971
    December 13th, 2016, 05:08 AM Go to last post
  16. Push data pairs into stack

    Started by snouppie, December 8th, 2016 06:36 AM
    vhdl
    • Replies: 8
    • Views: 953
    December 8th, 2016, 11:05 AM Go to last post
  17. Changing VHDL code to Schematics for download on DE2 board

    Started by Hozan677, November 29th, 2016 11:51 AM
    • Replies: 3
    • Views: 611
    November 30th, 2016, 06:14 AM Go to last post
  18. Sd card writing

    Started by phd.taha, November 26th, 2016 11:06 AM
    • Replies: 0
    • Views: 420
    November 26th, 2016, 11:06 AM Go to last post
  19. Fpga adc

    Started by assuero, November 23rd, 2016 09:08 PM
    adc, fpga, vhdl
    • Replies: 1
    • Views: 706
    November 23rd, 2016, 11:37 PM Go to last post
  20. latency in 1 port ram help

    Started by zhbai, November 20th, 2016 09:19 AM
    • Replies: 3
    • Views: 620
    November 22nd, 2016, 10:22 AM Go to last post
  21. VGA - output of a graphic not stable

    Started by orPoG, November 18th, 2016 07:51 AM
    • Replies: 2
    • Views: 701
    November 20th, 2016, 06:19 AM Go to last post
    • Replies: 4
    • Views: 670
    November 19th, 2016, 04:34 AM Go to last post
  22. Question about 1 port ram

    Started by zhbai, November 17th, 2016 11:28 AM
    quartus, single port ram, vhdl
    • Replies: 3
    • Views: 650
    November 17th, 2016, 11:12 PM Go to last post
  23. Question about component and packag

    Started by zhbai, November 17th, 2016 05:08 PM
    • Replies: 0
    • Views: 349
    November 17th, 2016, 05:08 PM Go to last post
  24. Post how to incorporate 2 cycles of latency

    Started by croat25, November 17th, 2016 09:10 AM
    mux, vhdl
    • Replies: 1
    • Views: 542
    November 17th, 2016, 11:00 AM Go to last post
    • Replies: 0
    • Views: 428
    November 11th, 2016, 05:48 AM Go to last post
  25. ieee.fixed_pkg in Quartus Prime 16.0 Lite Edition

    Started by clkEVENT, November 9th, 2016 11:04 PM
    fixed_pkg, quartus 16.0, vhdl 2008
    • Replies: 6
    • Views: 831
    November 10th, 2016, 03:33 AM Go to last post
    • Replies: 12
    • Views: 2,358
    November 2nd, 2016, 01:21 AM Go to last post
  26. Detecting a tansition in a signal

    Started by stephen@postec.co.nz, October 31st, 2016 01:54 PM
    • Replies: 2
    • Views: 466
    November 1st, 2016, 01:57 PM Go to last post
  27. Initializing issues with DE2 -DM9KA

    Started by LegendaryHeis1, October 23rd, 2016 12:24 PM
    • Replies: 2
    • Views: 579
    October 27th, 2016, 09:29 AM Go to last post

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