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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:52 PM
    • Replies: 6
    • Views: 45,861
    October 28th, 2015, 12:36 PM Go to last post
  1. Call a function from a function in VHDL

    Started by abenitez, October 13th, 2017 05:36 AM
    • Replies: 9
    • Views: 366
    October 16th, 2017, 08:47 AM Go to last post
  2. Unhappy Mod5 Counter

    Started by antonio.abela, October 14th, 2017 02:45 AM
    • Replies: 1
    • Views: 165
    October 16th, 2017, 02:27 AM Go to last post
  3. High-Z on Differential Port

    Started by afronteau, October 13th, 2017 05:55 AM
    an754, differential, high-z, mipi
    • Replies: 1
    • Views: 181
    October 14th, 2017, 01:40 AM Go to last post
  4. Combinational Loop In VHDL synthesis

    Started by Reza M. Shahshahani, October 3rd, 2017 06:22 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 786
    October 9th, 2017, 07:33 PM Go to last post
  5. How to use Shared Variable

    Started by wanjoe, March 2nd, 2017 03:55 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 3,795
    October 6th, 2017, 06:32 AM Go to last post
  6. Asynchronous FIFO

    Started by fm1990, October 6th, 2017 02:50 AM
    • Replies: 1
    • Views: 248
    October 6th, 2017, 04:59 AM Go to last post
  7. Cascaded Interpolation Filter and Restricted Fmax

    Started by shauk, July 19th, 2017 01:32 AM
    cascadefilter
    • Replies: 5
    • Views: 1,298
    October 4th, 2017, 08:15 PM Go to last post
  8. Adjustable frequency generator

    Started by kaamil115, September 23rd, 2017 03:59 AM
    • Replies: 5
    • Views: 763
    September 24th, 2017, 03:29 PM Go to last post
  9. Unhappy Implement mux using for loop

    Started by JeanValjean, September 15th, 2017 12:32 AM
    loop, mux, synthesis
    • Replies: 8
    • Views: 949
    September 16th, 2017, 12:49 AM Go to last post
  10. problem with type matching

    Started by lukasliekens, September 13th, 2017 10:35 AM
    component, instantiation, integer, modelsim, type
    • Replies: 6
    • Views: 718
    September 15th, 2017, 09:51 AM Go to last post
  11. using typedef intput argument for function

    Started by bienle, September 13th, 2017 05:16 AM
    vhdl; function;
    • Replies: 3
    • Views: 535
    September 13th, 2017, 10:56 PM Go to last post
  12. Question VHDL Model for MIPS Processor

    Started by irontitan76, May 3rd, 2013 09:47 PM
    4stage, mips, pipelined
    • Replies: 3
    • Views: 32,145
    September 12th, 2017, 10:43 AM Go to last post
  13. Problem with resolving signals in vhdl

    Started by lukasliekens, September 6th, 2017 10:00 AM
    integer, resolving signals, testbench, unresolved, vhdl
    • Replies: 6
    • Views: 904
    September 11th, 2017, 12:16 PM Go to last post
    • Replies: 1
    • Views: 426
    September 10th, 2017, 08:00 AM Go to last post
  14. how to calculate sin inverse (ARCSIN) in VHDL?

    Started by G.Ornil, June 29th, 2017 01:28 AM
    2 Pages
    1 2
    vhdl arcsin
    • Replies: 10
    • Views: 3,071
    September 4th, 2017, 04:53 PM Go to last post
    • Replies: 2
    • Views: 745
    September 4th, 2017, 04:47 PM Go to last post
  15. Question frequency meter on cyclone IV E ,without display frequency

    Started by SmErT, August 21st, 2017 02:46 AM
    • Replies: 5
    • Views: 1,019
    August 22nd, 2017, 12:11 AM Go to last post
  16. StateMachine States in SignalTAP

    Started by fpgaengineerfrankfurt, August 15th, 2017 03:42 AM
    • Replies: 2
    • Views: 730
    August 15th, 2017, 08:46 PM Go to last post
    • Replies: 2
    • Views: 869
    August 4th, 2017, 02:45 AM Go to last post
  17. LFSR doesn't generate random values during simulation Ask

    Started by learn1, August 3rd, 2017 11:06 PM
    galois, lfsr, vhdl
    • Replies: 7
    • Views: 1,206
    August 4th, 2017, 12:21 AM Go to last post
  18. Another 10482 VHDL error

    Started by jnuckols, July 31st, 2017 04:13 AM
    10482
    • Replies: 2
    • Views: 773
    July 31st, 2017, 05:19 AM Go to last post
  19. VHDL "+" Operator

    Started by qh9433q, July 18th, 2017 03:59 PM
    • Replies: 1
    • Views: 666
    July 18th, 2017, 10:28 PM Go to last post
  20. Compare two byte arrays

    Started by john7, July 11th, 2017 10:54 PM
    • Replies: 6
    • Views: 1,311
    July 12th, 2017, 03:44 AM Go to last post
  21. String operation

    Started by john7, July 11th, 2017 04:14 AM
    • Replies: 5
    • Views: 1,097
    July 11th, 2017, 07:21 AM Go to last post
    • Replies: 1
    • Views: 930
    July 10th, 2017, 05:23 AM Go to last post
  22. String parser

    Started by john7, July 2nd, 2017 11:25 PM
    • Replies: 3
    • Views: 977
    July 4th, 2017, 01:57 AM Go to last post
  23. Ones counter using numeric_std inside process

    Started by sdytfx, June 27th, 2017 01:31 PM
    • Replies: 3
    • Views: 1,026
    June 27th, 2017, 10:26 PM Go to last post
  24. 10500 syntax Error

    Started by adb05, June 26th, 2017 06:17 AM
    • Replies: 7
    • Views: 1,350
    June 26th, 2017, 09:18 AM Go to last post
  25. performance problems with std_logic_vector

    Started by cjr9968, June 23rd, 2017 03:40 PM
    de2-115, std_logic_vector, vhdl
    • Replies: 1
    • Views: 889
    June 23rd, 2017, 09:58 PM Go to last post
    • Replies: 5
    • Views: 1,598
    June 23rd, 2017, 03:43 PM Go to last post

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