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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:52 PM
    • Replies: 6
    • Views: 43,301
    October 28th, 2015, 12:36 PM Go to last post
  1. Signal not assigned in init state

    Started by PuqmaStar, March 21st, 2017 08:20 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 508
    Yesterday, 10:40 PM Go to last post
  2. VHDL "Quantum" bug

    Started by javieralso, March 17th, 2017 04:41 AM
    • Replies: 4
    • Views: 118
    March 21st, 2017, 07:07 AM Go to last post
  3. UART VDHL code not working getting only garbage values

    Started by G.Ornil, March 17th, 2017 01:26 AM
    de0-nani-soc, fpga cyclone v, uart, vhdl
    • Replies: 1
    • Views: 83
    March 20th, 2017, 01:08 PM Go to last post
  4. Edge detection asynchronous signal fails

    Started by PuqmaStar, March 18th, 2017 06:15 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 171
    March 20th, 2017, 12:12 AM Go to last post
  5. Bi Directional pins

    Started by tmny277, February 18th, 2017 01:20 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 363
    March 18th, 2017, 02:49 PM Go to last post
  6. VHDL 2008: Error (10500) in conditional assignment

    Started by arne, March 13th, 2017 01:49 AM
    vhdl-2008
    • Replies: 5
    • Views: 150
    March 13th, 2017, 03:00 AM Go to last post
  7. Type problem? Compiler doesn't help me!

    Started by Josť, March 9th, 2017 10:06 AM
    • Replies: 5
    • Views: 201
    March 10th, 2017, 10:43 PM Go to last post
  8. How to use Shared Variable

    Started by wanjoe, March 2nd, 2017 03:55 AM
    • Replies: 1
    • Views: 132
    March 8th, 2017, 10:09 AM Go to last post
    • Replies: 2
    • Views: 154
    March 6th, 2017, 10:19 AM Go to last post
  9. Question Long FIR Filter

    Started by shauk, March 6th, 2017 02:06 AM
    • Replies: 5
    • Views: 151
    March 6th, 2017, 03:32 AM Go to last post
  10. Interrupt detection

    Started by john7, March 2nd, 2017 12:13 AM
    • Replies: 1
    • Views: 108
    March 2nd, 2017, 03:33 AM Go to last post
  11. Buffering a signal.

    Started by john7, March 1st, 2017 02:36 AM
    • Replies: 8
    • Views: 248
    March 1st, 2017, 07:31 AM Go to last post
  12. When to reset a signal.

    Started by john7, February 28th, 2017 06:04 AM
    • Replies: 5
    • Views: 215
    February 28th, 2017, 11:15 PM Go to last post
  13. Can't resolve multiple constant drivers

    Started by john7, February 27th, 2017 12:45 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 273
    February 28th, 2017, 02:02 AM Go to last post
  14. Unhappy up counter needs fixing - confused . simple question

    Started by FINCH1, February 22nd, 2017 09:35 PM
    2 Pages
    1 2
    • Replies: 17
    • Views: 477
    February 27th, 2017, 10:37 AM Go to last post
  15. floating point number

    Started by yossiwf, January 15th, 2017 04:26 AM
    • Replies: 9
    • Views: 442
    February 23rd, 2017, 01:47 PM Go to last post
  16. Problem converting to integer

    Started by john7, February 20th, 2017 12:36 AM
    • Replies: 4
    • Views: 175
    February 20th, 2017, 04:02 AM Go to last post
  17. Write a lot of data

    Started by john7, February 14th, 2017 10:57 PM
    • Replies: 4
    • Views: 239
    February 15th, 2017, 02:32 AM Go to last post
  18. Displaying Binary/Hex Output on VGA

    Started by stark123, February 6th, 2017 06:50 AM
    quartus, vga, vhdl
    • Replies: 2
    • Views: 217
    February 12th, 2017, 03:53 AM Go to last post
  19. Assigning value to 7 bits output buffer?

    Started by sbesozzi, February 9th, 2017 03:54 PM
    • Replies: 4
    • Views: 245
    February 10th, 2017, 10:15 AM Go to last post
  20. VHDL help for using built in Comparators

    Started by zhbai, February 9th, 2017 02:28 PM
    • Replies: 3
    • Views: 179
    February 9th, 2017, 11:24 PM Go to last post
  21. IEEE library showing up in red

    Started by sbesozzi, February 9th, 2017 02:56 PM
    ieee, library, quartus, vhdl
    • Replies: 2
    • Views: 150
    February 9th, 2017, 03:48 PM Go to last post
  22. Using a SPI module.

    Started by john7, February 5th, 2017 10:13 PM
    • Replies: 6
    • Views: 291
    February 6th, 2017, 11:45 AM Go to last post
  23. pulse counting

    Started by FPGApadawan, February 2nd, 2017 01:21 PM
    • Replies: 7
    • Views: 331
    February 4th, 2017, 01:37 PM Go to last post
  24. Question Relational operators

    Started by FPGApadawan, January 28th, 2017 04:35 AM
    relational operators
    • Replies: 4
    • Views: 318
    January 28th, 2017, 12:48 PM Go to last post
  25. output forced unknown

    Started by pabloemma, January 12th, 2017 09:36 AM
    • Replies: 2
    • Views: 206
    January 26th, 2017, 12:16 PM Go to last post
  26. Expression has 32 elements ; expected 16

    Started by Sfato, January 24th, 2017 07:38 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 495
    January 25th, 2017, 04:57 AM Go to last post
  27. How to properly connect PLL in Cyclone V?

    Started by adam.trhon, January 23rd, 2017 05:52 AM
    • Replies: 1
    • Views: 205
    January 23rd, 2017, 11:55 PM Go to last post
  28. Suggesting a testbench for a design

    Started by Hozan677, January 10th, 2017 11:20 AM
    • Replies: 2
    • Views: 230
    January 20th, 2017, 03:44 AM Go to last post
  29. problem (?) using shared variables

    Started by Jaraqui, July 26th, 2013 11:40 AM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 32,301
    January 20th, 2017, 03:40 AM Go to last post

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