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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:52 PM
    • Replies: 6
    • Views: 43,156
    October 28th, 2015, 01:36 PM Go to last post
  1. Bi Directional pins

    Started by tmny277, February 18th, 2017 02:20 PM
    • Replies: 3
    • Views: 125
    Yesterday, 12:48 PM Go to last post
  2. Problem converting to integer

    Started by john7, Yesterday 01:36 AM
    • Replies: 4
    • Views: 81
    Yesterday, 05:02 AM Go to last post
  3. Write a lot of data

    Started by john7, February 14th, 2017 11:57 PM
    • Replies: 4
    • Views: 161
    February 15th, 2017, 03:32 AM Go to last post
  4. Displaying Binary/Hex Output on VGA

    Started by stark123, February 6th, 2017 07:50 AM
    quartus, vga, vhdl
    • Replies: 2
    • Views: 145
    February 12th, 2017, 04:53 AM Go to last post
  5. Assigning value to 7 bits output buffer?

    Started by sbesozzi, February 9th, 2017 04:54 PM
    • Replies: 4
    • Views: 158
    February 10th, 2017, 11:15 AM Go to last post
  6. VHDL help for using built in Comparators

    Started by zhbai, February 9th, 2017 03:28 PM
    • Replies: 3
    • Views: 103
    February 10th, 2017, 12:24 AM Go to last post
  7. IEEE library showing up in red

    Started by sbesozzi, February 9th, 2017 03:56 PM
    ieee, library, quartus, vhdl
    • Replies: 2
    • Views: 73
    February 9th, 2017, 04:48 PM Go to last post
  8. Using a SPI module.

    Started by john7, February 5th, 2017 11:13 PM
    • Replies: 6
    • Views: 211
    February 6th, 2017, 12:45 PM Go to last post
  9. pulse counting

    Started by FPGApadawan, February 2nd, 2017 02:21 PM
    • Replies: 7
    • Views: 228
    February 4th, 2017, 02:37 PM Go to last post
  10. Question Relational operators

    Started by FPGApadawan, January 28th, 2017 05:35 AM
    relational operators
    • Replies: 4
    • Views: 224
    January 28th, 2017, 01:48 PM Go to last post
  11. output forced unknown

    Started by pabloemma, January 12th, 2017 10:36 AM
    • Replies: 2
    • Views: 146
    January 26th, 2017, 01:16 PM Go to last post
  12. Expression has 32 elements ; expected 16

    Started by Sfato, January 24th, 2017 08:38 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 314
    January 25th, 2017, 05:57 AM Go to last post
  13. How to properly connect PLL in Cyclone V?

    Started by adam.trhon, January 23rd, 2017 06:52 AM
    • Replies: 1
    • Views: 147
    January 24th, 2017, 12:55 AM Go to last post
  14. Suggesting a testbench for a design

    Started by Hozan677, January 10th, 2017 12:20 PM
    • Replies: 2
    • Views: 168
    January 20th, 2017, 04:44 AM Go to last post
  15. problem (?) using shared variables

    Started by Jaraqui, July 26th, 2013 12:40 PM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 32,042
    January 20th, 2017, 04:40 AM Go to last post
  16. Newbie vs VHDL: season 01 episode 01

    Started by Sniffer, January 18th, 2017 07:15 AM
    vhdl
    • Replies: 7
    • Views: 312
    January 19th, 2017, 05:18 AM Go to last post
  17. Question Matrix in vhdl

    Started by Yamini, January 17th, 2017 09:35 PM
    • Replies: 1
    • Views: 134
    January 17th, 2017, 11:48 PM Go to last post
  18. floating point number

    Started by yossiwf, January 15th, 2017 05:26 AM
    • Replies: 6
    • Views: 300
    January 16th, 2017, 08:16 AM Go to last post
  19. File not simulating with ModelSim-Altera

    Started by Hozan677, January 11th, 2017 11:32 AM
    • Replies: 5
    • Views: 276
    January 16th, 2017, 07:41 AM Go to last post
  20. Dual Clock FIFO Implementation VHDL

    Started by abrownlie, January 9th, 2017 07:55 AM
    • Replies: 4
    • Views: 257
    January 16th, 2017, 12:49 AM Go to last post
  21. Shift constant by variable amount

    Started by sstrell, January 14th, 2017 09:07 AM
    • Replies: 2
    • Views: 155
    January 14th, 2017, 03:45 PM Go to last post
  22. Can't Simulate Buffer port in ModelSim

    Started by Hozan677, January 9th, 2017 08:35 AM
    • Replies: 2
    • Views: 154
    January 9th, 2017, 09:00 AM Go to last post
  23. MIDI Manager

    Started by FPGApadawan, January 7th, 2017 12:54 PM
    • Replies: 2
    • Views: 168
    January 8th, 2017, 06:04 AM Go to last post
  24. Websites providing professional help

    Started by Hozan677, January 4th, 2017 12:02 PM
    • Replies: 5
    • Views: 320
    January 7th, 2017, 06:34 PM Go to last post
  25. Frequency division for use in an 8x1 multiplexer

    Started by Hozan677, December 24th, 2016 07:44 AM
    • Replies: 3
    • Views: 272
    January 1st, 2017, 10:16 AM Go to last post
  26. UART issue

    Started by FPGApadawan, December 29th, 2016 11:08 AM
    • Replies: 5
    • Views: 307
    December 30th, 2016, 01:31 PM Go to last post
  27. using lpm_counter to divide a clock by any No

    Started by Hozan677, December 22nd, 2016 09:21 AM
    • Replies: 4
    • Views: 325
    December 29th, 2016, 07:53 AM Go to last post
  28. Question about True Dual Port RAM

    Started by snouppie, December 18th, 2016 03:52 AM
    • Replies: 6
    • Views: 463
    December 23rd, 2016, 01:33 PM Go to last post
  29. How to use a for loop for repetitive timed actions

    Started by mafstoffer, December 16th, 2016 03:08 PM
    • Replies: 6
    • Views: 425
    December 19th, 2016, 03:23 PM Go to last post
  30. One port ram question

    Started by zhbai, December 17th, 2016 01:42 PM
    on chip memory, one port memory, vhdl
    • Replies: 3
    • Views: 290
    December 19th, 2016, 02:25 PM Go to last post

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