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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 547
    • Posts: 2,061
  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 231
    • Posts: 597
  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    Forum Statistics:

    • Threads: 82
    • Posts: 273
  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    Forum Statistics:

    • Threads: 93
    • Posts: 354
  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 11:29 AM
    • Replies: 0
    • Views: 11,468
    January 27th, 2015, 11:29 AM Go to last post
  1. Touch LCD for DE10 nano and compare with BeagleBoard

    Started by egywell, January 29th, 2018 06:30 AM
    • Replies: 2
    • Views: 658
    February 12th, 2018, 10:21 PM Go to last post
  2. [Arria 10] Implementation of a PCI Express "Host" solution

    Started by remhi.ch, February 8th, 2018 05:25 AM
    arria, express, host, pci, rootcomplex
    • Replies: 0
    • Views: 811
    February 8th, 2018, 05:25 AM Go to last post
  3. Cyclone V SoC using LTC2978 sensor for voltage monitoring

    Started by nekuss1, February 5th, 2018 06:58 AM
    • Replies: 3
    • Views: 676
    February 6th, 2018, 05:52 AM Go to last post
  4. EM2130L Regulator with external Sync clock

    Started by bhavishya aj, February 5th, 2018 04:50 AM
    • Replies: 1
    • Views: 511
    February 5th, 2018, 08:09 PM Go to last post
  5. NIOS GPIO and Metastability question

    Started by berretto77, February 5th, 2018 12:39 AM
    nios gpio metastability
    • Replies: 0
    • Views: 383
    February 5th, 2018, 12:39 AM Go to last post
  6. Cyclone V SoC doubt

    Started by joel.sanchez, January 27th, 2018 02:03 AM
    arm, cyclone v, fpga, soc
    • Replies: 4
    • Views: 895
    January 29th, 2018, 11:46 AM Go to last post
  7. Cyclone V SoC - Time execution function - Cycle count

    Started by Remy ASTIER, January 20th, 2015 11:58 PM
    • Replies: 4
    • Views: 7,072
    January 29th, 2018, 07:58 AM Go to last post
    • Replies: 2
    • Views: 844
    January 17th, 2018, 01:45 PM Go to last post
  8. Question HPS SPI Master with more than 4 Slave Selects

    Started by Designer777, January 12th, 2018 05:42 AM
    arria 10, slave select, soc, spi, spi master controller
    • Replies: 1
    • Views: 679
    January 13th, 2018, 07:20 PM Go to last post
    • Replies: 7
    • Views: 1,306
    January 8th, 2018, 09:44 AM Go to last post
  9. Memory map error in software program

    Started by karthik.k, January 7th, 2018 08:31 PM
    • Replies: 0
    • Views: 748
    January 7th, 2018, 08:31 PM Go to last post
  10. Set initial value at beginning

    Started by Doug314, December 30th, 2017 07:25 AM
    • Replies: 4
    • Views: 1,132
    January 1st, 2018, 06:15 AM Go to last post
    • Replies: 2
    • Views: 995
    December 14th, 2017, 01:20 AM Go to last post
  11. Address Span Extender

    Started by MUTHUVENKATESH, November 30th, 2017 01:08 AM
    • Replies: 1
    • Views: 1,141
    December 10th, 2017, 02:42 AM Go to last post
  12. UART encoding issues

    Started by koded, December 8th, 2017 08:16 AM
    • Replies: 1
    • Views: 784
    December 9th, 2017, 01:54 AM Go to last post
  13. Fpga -qt

    Started by KANZALI, December 3rd, 2017 03:22 AM
    • Replies: 1
    • Views: 837
    December 3rd, 2017, 06:23 PM Go to last post
    • Replies: 1
    • Views: 991
    December 1st, 2017, 10:46 PM Go to last post
  14. Tristate bridge controller parameters

    Started by berretto77, November 30th, 2017 04:54 AM
    • Replies: 0
    • Views: 752
    November 30th, 2017, 04:54 AM Go to last post
  15. Verify functionality of design in arria 10 SoC

    Started by karthik.k, November 29th, 2017 12:50 AM
    • Replies: 0
    • Views: 1,183
    November 29th, 2017, 12:50 AM Go to last post
  16. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 01:32 PM
    • Replies: 2
    • Views: 997
    November 20th, 2017, 10:08 PM Go to last post
    • Replies: 4
    • Views: 2,788
    November 18th, 2017, 08:08 PM Go to last post
  17. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 03:21 AM
    • Replies: 3
    • Views: 1,068
    November 13th, 2017, 09:06 AM Go to last post
    • Replies: 2
    • Views: 1,111
    November 12th, 2017, 12:13 PM Go to last post
  18. Interfacing uOLED Display to Cyclone V HPS

    Started by kba, November 6th, 2017 08:04 AM
    • Replies: 1
    • Views: 796
    November 8th, 2017, 10:22 PM Go to last post
  19. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 06:30 PM
    • Replies: 4
    • Views: 1,910
    November 7th, 2017, 03:21 AM Go to last post
    • Replies: 1
    • Views: 948
    November 2nd, 2017, 10:45 AM Go to last post
  20. DMA read timeout while using PL330?

    Started by Brillow, May 12th, 2016 06:44 AM
    • Replies: 4
    • Views: 3,416
    October 27th, 2017, 12:39 PM Go to last post
    • Replies: 4
    • Views: 3,222
    October 27th, 2017, 06:43 AM Go to last post
  21. Question FPGA to SDRAM AXI Transfer

    Started by ariefgrand, October 6th, 2017 07:04 AM
    arria, axi, sdram
    • Replies: 3
    • Views: 1,545
    October 27th, 2017, 12:21 AM Go to last post
    • Replies: 0
    • Views: 722
    October 23rd, 2017, 11:26 PM Go to last post

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