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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 550
    • Posts: 2,076

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    Nios ii Go to last post

    May 17th, 2018, 09:47 PM

  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 233
    • Posts: 605
  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    • Threads: 84
    • Posts: 276

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  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    • Threads: 93
    • Posts: 354

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  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 11:29 AM
    • Replies: 0
    • Views: 11,745
    January 27th, 2015, 11:29 AM Go to last post
  1. Tristate bridge controller parameters

    Started by berretto77, November 30th, 2017 04:54 AM
    • Replies: 0
    • Views: 817
    November 30th, 2017, 04:54 AM Go to last post
  2. Verify functionality of design in arria 10 SoC

    Started by karthik.k, November 29th, 2017 12:50 AM
    • Replies: 0
    • Views: 1,251
    November 29th, 2017, 12:50 AM Go to last post
  3. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 01:32 PM
    • Replies: 2
    • Views: 1,079
    November 20th, 2017, 10:08 PM Go to last post
    • Replies: 4
    • Views: 2,933
    November 18th, 2017, 08:08 PM Go to last post
  4. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 03:21 AM
    • Replies: 3
    • Views: 1,240
    November 13th, 2017, 09:06 AM Go to last post
  5. Interfacing uOLED Display to Cyclone V HPS

    Started by kba, November 6th, 2017 08:04 AM
    • Replies: 1
    • Views: 850
    November 8th, 2017, 10:22 PM Go to last post
  6. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 06:30 PM
    • Replies: 4
    • Views: 2,004
    November 7th, 2017, 03:21 AM Go to last post
    • Replies: 1
    • Views: 1,037
    November 2nd, 2017, 10:45 AM Go to last post
  7. DMA read timeout while using PL330?

    Started by Brillow, May 12th, 2016 06:44 AM
    • Replies: 4
    • Views: 3,540
    October 27th, 2017, 12:39 PM Go to last post
    • Replies: 4
    • Views: 3,351
    October 27th, 2017, 06:43 AM Go to last post
  8. Question FPGA to SDRAM AXI Transfer

    Started by ariefgrand, October 6th, 2017 07:04 AM
    arria, axi, sdram
    • Replies: 3
    • Views: 1,676
    October 27th, 2017, 12:21 AM Go to last post
    • Replies: 0
    • Views: 799
    October 23rd, 2017, 11:26 PM Go to last post
  9. Getting Error with DE0-nano-soc [making u-boot.img]

    Started by jongyun23, August 31st, 2017 10:24 PM
    • Replies: 2
    • Views: 1,535
    October 16th, 2017, 12:43 AM Go to last post
  10. Read DDR to file using HPS2FPGA

    Started by ela05jdc, September 8th, 2017 09:12 AM
    arrow, hps, hps2fpga, soc, sockit
    • Replies: 1
    • Views: 1,333
    October 16th, 2017, 12:33 AM Go to last post
  11. Connect FFT IP core and QSYS

    Started by ezequiel, October 10th, 2017 03:53 AM
    • Replies: 0
    • Views: 934
    October 10th, 2017, 03:53 AM Go to last post
  12. Disable FPU on Arria10 SoC FPGA

    Started by karthik.k, August 28th, 2017 11:17 PM
    • Replies: 6
    • Views: 2,673
    October 8th, 2017, 02:15 AM Go to last post
  13. make_sdimage.py creates invalid ext3 partition

    Started by billr, December 13th, 2016 08:20 PM
    • Replies: 1
    • Views: 1,781
    September 27th, 2017, 02:12 AM Go to last post
  14. Question Linux Console with framebuffer on DE10-nano SOC

    Started by yazbek, September 24th, 2017 11:39 PM
    • Replies: 0
    • Views: 1,121
    September 24th, 2017, 11:39 PM Go to last post
  15. DE1-SoC Interfacing with ADXL345 3 Axis Accelerometer [I2C]

    Started by XXRyanXXL, September 14th, 2017 08:46 AM
    • Replies: 1
    • Views: 1,240
    September 23rd, 2017, 08:13 AM Go to last post
  16. Unhappy YoctoPlugin SoCKit Altera Cyclone 5

    Started by geogrebust, September 22nd, 2016 05:46 AM
    • Replies: 1
    • Views: 2,094
    September 15th, 2017, 06:47 AM Go to last post
    • Replies: 0
    • Views: 974
    September 7th, 2017, 12:24 PM Go to last post
    • Replies: 0
    • Views: 932
    August 31st, 2017, 10:20 PM Go to last post
  17. Uart Baud Rate Drop

    Started by stefanri, August 17th, 2017 07:09 AM
    • Replies: 4
    • Views: 1,478
    August 22nd, 2017, 09:32 AM Go to last post
  18. SPI communication

    Started by seongjinkim, August 22nd, 2017 03:42 AM
    • Replies: 0
    • Views: 838
    August 22nd, 2017, 03:42 AM Go to last post
  19. Altera avalon I2C

    Started by kgandhi0408, August 18th, 2017 03:39 AM
    • Replies: 1
    • Views: 1,305
    August 18th, 2017, 09:03 PM Go to last post
  20. Fixed-link Feature

    Started by MartinFeng_Cytech, August 17th, 2017 12:23 AM
    • Replies: 0
    • Views: 1,061
    August 17th, 2017, 12:23 AM Go to last post
  21. Questions about SOC FPGA Preloader and device tree

    Started by OmranAbazid, May 23rd, 2017 02:40 PM
    • Replies: 9
    • Views: 4,483
    August 1st, 2017, 12:28 AM Go to last post
  22. Qsys Custom Peripheral Memory Mapping

    Started by FlipFlop, July 26th, 2017 08:53 PM
    custom peripheral, interrupt, nios, qsys
    • Replies: 2
    • Views: 1,596
    July 28th, 2017, 12:59 PM Go to last post
  23. Soc simulation in VHDL

    Started by romainht, July 27th, 2017 11:10 PM
    modelsim, vhdl
    • Replies: 2
    • Views: 1,376
    July 28th, 2017, 01:38 AM Go to last post
  24. Datails about DK-START-5AGXB3N

    Started by Pierre9258, July 26th, 2017 11:25 PM
    • Replies: 3
    • Views: 1,334
    July 28th, 2017, 01:13 AM Go to last post

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