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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 525
    • Posts: 1,970

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  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 217
    • Posts: 569
  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    • Threads: 73
    • Posts: 258

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  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    • Threads: 88
    • Posts: 335

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  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 12:29 PM
    • Replies: 0
    • Views: 10,639
    January 27th, 2015, 12:29 PM Go to last post
    • Replies: 0
    • Views: 2
    Today, 01:25 PM Go to last post
    • Replies: 2
    • Views: 240
    December 14th, 2017, 02:20 AM Go to last post
  1. creating custom multiple registers

    Started by smruthi, December 12th, 2017 05:00 AM
    custom component, nios2
    • Replies: 3
    • Views: 271
    December 12th, 2017, 04:46 PM Go to last post
  2. Address Span Extender

    Started by MUTHUVENKATESH, November 30th, 2017 02:08 AM
    • Replies: 1
    • Views: 333
    December 10th, 2017, 03:42 AM Go to last post
  3. UART encoding issues

    Started by koded, December 8th, 2017 09:16 AM
    • Replies: 1
    • Views: 193
    December 9th, 2017, 02:54 AM Go to last post
  4. Fpga -qt

    Started by KANZALI, December 3rd, 2017 04:22 AM
    • Replies: 1
    • Views: 291
    December 3rd, 2017, 07:23 PM Go to last post
    • Replies: 1
    • Views: 360
    December 1st, 2017, 11:46 PM Go to last post
  5. Tristate bridge controller parameters

    Started by berretto77, November 30th, 2017 05:54 AM
    • Replies: 0
    • Views: 296
    November 30th, 2017, 05:54 AM Go to last post
  6. Verify functionality of design in arria 10 SoC

    Started by karthik.k, November 29th, 2017 01:50 AM
    • Replies: 0
    • Views: 733
    November 29th, 2017, 01:50 AM Go to last post
  7. Cyclone V SOC F2S Arbitration

    Started by shaiko, November 24th, 2017 04:14 AM
    • Replies: 0
    • Views: 368
    November 24th, 2017, 04:14 AM Go to last post
  8. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 02:32 PM
    • Replies: 2
    • Views: 475
    November 20th, 2017, 11:08 PM Go to last post
    • Replies: 4
    • Views: 1,821
    November 18th, 2017, 09:08 PM Go to last post
  9. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 04:21 AM
    • Replies: 3
    • Views: 428
    November 13th, 2017, 10:06 AM Go to last post
    • Replies: 2
    • Views: 514
    November 12th, 2017, 01:13 PM Go to last post
  10. Qsys Custom component Error

    Started by Marco Lobba, August 8th, 2017 08:29 AM
    • Replies: 3
    • Views: 1,180
    November 10th, 2017, 03:49 AM Go to last post
  11. Interfacing uOLED Display to Cyclone V HPS

    Started by kba, November 6th, 2017 09:04 AM
    • Replies: 1
    • Views: 362
    November 8th, 2017, 11:22 PM Go to last post
  12. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 07:30 PM
    • Replies: 4
    • Views: 1,173
    November 7th, 2017, 04:21 AM Go to last post
    • Replies: 1
    • Views: 458
    November 2nd, 2017, 11:45 AM Go to last post
  13. mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

    Started by slh47, October 30th, 2017 02:38 AM
    • Replies: 2
    • Views: 467
    October 30th, 2017, 11:52 AM Go to last post
  14. DMA read timeout while using PL330?

    Started by Brillow, May 12th, 2016 07:44 AM
    • Replies: 4
    • Views: 2,638
    October 27th, 2017, 01:39 PM Go to last post
    • Replies: 4
    • Views: 2,323
    October 27th, 2017, 07:43 AM Go to last post
  15. Question FPGA to SDRAM AXI Transfer

    Started by ariefgrand, October 6th, 2017 08:04 AM
    arria, axi, sdram
    • Replies: 3
    • Views: 904
    October 27th, 2017, 01:21 AM Go to last post
    • Replies: 0
    • Views: 353
    October 24th, 2017, 12:26 AM Go to last post
  16. Getting Error with DE0-nano-soc [making u-boot.img]

    Started by jongyun23, August 31st, 2017 11:24 PM
    • Replies: 2
    • Views: 876
    October 16th, 2017, 01:43 AM Go to last post
  17. Read DDR to file using HPS2FPGA

    Started by ela05jdc, September 8th, 2017 10:12 AM
    arrow, hps, hps2fpga, soc, sockit
    • Replies: 1
    • Views: 800
    October 16th, 2017, 01:33 AM Go to last post
  18. Connect FFT IP core and QSYS

    Started by ezequiel, October 10th, 2017 04:53 AM
    • Replies: 0
    • Views: 519
    October 10th, 2017, 04:53 AM Go to last post
  19. Disable FPU on Arria10 SoC FPGA

    Started by karthik.k, August 29th, 2017 12:17 AM
    • Replies: 6
    • Views: 1,749
    October 8th, 2017, 03:15 AM Go to last post
  20. make_sdimage.py creates invalid ext3 partition

    Started by billr, December 13th, 2016 09:20 PM
    • Replies: 1
    • Views: 1,238
    September 27th, 2017, 03:12 AM Go to last post
  21. Question Linux Console with framebuffer on DE10-nano SOC

    Started by yazbek, September 25th, 2017 12:39 AM
    • Replies: 0
    • Views: 622
    September 25th, 2017, 12:39 AM Go to last post
  22. DE1-SoC Interfacing with ADXL345 3 Axis Accelerometer [I2C]

    Started by XXRyanXXL, September 14th, 2017 09:46 AM
    • Replies: 1
    • Views: 781
    September 23rd, 2017, 09:13 AM Go to last post

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