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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 03:36 PM
    • Replies: 0
    • Views: 11,188
    October 14th, 2014, 03:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 02:37 PM
    • Replies: 0
    • Views: 30,440
    July 19th, 2013, 02:37 PM Go to last post
    • Replies: 0
    • Views: 21
    Today, 04:00 AM Go to last post
  1. How to enable SDRAM ECC in the Qsys

    Started by mojcmos, September 26th, 2016 03:34 AM
    • Replies: 4
    • Views: 90
    September 26th, 2016, 11:49 PM Go to last post
  2. Altera Cyclone V SoC FPGA Development Kit GPIO chip numbering

    Started by eldorr, September 26th, 2016 10:54 PM
    • Replies: 0
    • Views: 33
    September 26th, 2016, 10:54 PM Go to last post
  3. Terasic SATA/SAS HSMC Card Reference Project for Cyclone V SOC

    Started by redd, January 28th, 2016 12:42 PM
    cyclone v, hsmc, reference design, sata
    • Replies: 1
    • Views: 536
    September 23rd, 2016, 01:34 AM Go to last post
  4. Question How to generate boardinfo (xml) files?

    Started by Kunal Patwardhan, September 22nd, 2016 10:43 PM
    boardinfo, cyclone v soc, device tree source, dts
    • Replies: 1
    • Views: 64
    September 22nd, 2016, 11:41 PM Go to last post
  5. High bandwidth data transfer between hps and fpga

    Started by mojcmos, September 8th, 2016 03:50 AM
    • Replies: 8
    • Views: 317
    September 21st, 2016, 06:10 PM Go to last post
    • Replies: 3
    • Views: 133
    September 21st, 2016, 05:33 PM Go to last post
  6. using h2f_axi_master

    Started by mojcmos, September 13th, 2016 10:11 PM
    • Replies: 0
    • Views: 92
    September 13th, 2016, 10:11 PM Go to last post
  7. How to Program Cyclone V SoC Dev Kit EPCQ256

    Started by kstolp, September 2nd, 2013 02:41 PM
    • Replies: 8
    • Views: 30,062
    September 12th, 2016, 05:12 AM Go to last post
  8. Cyclone V SoC Migration to Arria 10 SoC

    Started by johnie83, August 9th, 2016 07:10 AM
    arria 10, cyclone v
    • Replies: 1
    • Views: 190
    September 6th, 2016, 10:16 PM Go to last post
  9. need to License for ARM hard processor

    Started by mojcmos, August 28th, 2016 11:28 PM
    • Replies: 1
    • Views: 186
    September 6th, 2016, 10:09 PM Go to last post
  10. DE1-SoC HPS DDR3 Controller with UniPHY fitter error

    Started by Korn, April 10th, 2016 04:46 AM
    • Replies: 1
    • Views: 441
    September 6th, 2016, 07:29 PM Go to last post
    • Replies: 13
    • Views: 17,475
    August 31st, 2016, 09:56 AM Go to last post
    • Replies: 2
    • Views: 185
    August 25th, 2016, 09:43 PM Go to last post
  11. using the FPU on Cortex A9

    Started by stefmaster, December 10th, 2013 03:20 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 24,708
    August 16th, 2016, 07:15 AM Go to last post
  12. Question Problem when programming Cyclone V (DE1-SoC)

    Started by franerto, February 24th, 2016 11:57 PM
    cyclone v, de1, programming, soc
    • Replies: 5
    • Views: 1,042
    August 14th, 2016, 03:29 AM Go to last post
  13. Question about the FPGA 10/100 Ethernet (FPGA)

    Started by yeahnix, July 29th, 2013 05:33 PM
    • Replies: 5
    • Views: 29,910
    August 12th, 2016, 02:35 AM Go to last post
  14. SoC with DDR3: Fitter refuses to fit HPS_DM_0

    Started by jordanf, August 8th, 2016 08:04 AM
    • Replies: 4
    • Views: 275
    August 11th, 2016, 05:28 AM Go to last post
  15. Angry Trouble adding additional F2H_SDRAM Port

    Started by jliriano, November 7th, 2014 08:27 AM
    • Replies: 3
    • Views: 9,846
    August 9th, 2016, 05:04 PM Go to last post
  16. SOC Tools: Is Xlinx light-years ahead of Altera?

    Started by joe306, June 13th, 2016 06:12 AM
    • Replies: 2
    • Views: 446
    August 9th, 2016, 02:45 AM Go to last post
  17. Exclamation DS-5 debugger "run" or "start" option lead HPS to reset

    Started by serjjo, January 27th, 2015 05:12 AM
    2 Pages
    1 2
    debugger, ds-5
    • Replies: 11
    • Views: 6,547
    August 7th, 2016, 06:55 PM Go to last post
  18. Watchdog Problems with Cyclone V soc

    Started by DaveHorne, November 11th, 2013 05:54 AM
    watchdog soc hps
    • Replies: 1
    • Views: 23,812
    July 31st, 2016, 09:08 AM Go to last post
  19. Using HPS2FPGA from HPS point of view

    Started by Alb, July 27th, 2016 08:42 AM
    • Replies: 0
    • Views: 227
    July 27th, 2016, 08:42 AM Go to last post
  20. accelerate cyclone V

    Started by rjchokshi, July 12th, 2016 07:28 AM
    • Replies: 1
    • Views: 329
    July 21st, 2016, 01:02 PM Go to last post
  21. fast input registers routed over HPS Loan I/O Pins

    Started by tobiaswelti, June 27th, 2016 12:26 AM
    cyclone v, fast input register, hps loan i/o
    • Replies: 1
    • Views: 310
    July 21st, 2016, 01:00 PM Go to last post
  22. Arria 10 Soc FFT?

    Started by joe306, June 13th, 2016 01:36 PM
    • Replies: 1
    • Views: 347
    July 21st, 2016, 12:54 PM Go to last post
    • Replies: 1
    • Views: 283
    July 14th, 2016, 11:17 PM Go to last post
  23. DE1-SOC working without DS5 tool

    Started by sherif123, June 30th, 2016 03:16 AM
    • Replies: 4
    • Views: 410
    July 1st, 2016, 10:38 PM Go to last post
  24. Debugging FPGA Timer on AXI bus generates RESET EXCEPTION

    Started by brancht, June 30th, 2016 10:58 AM
    • Replies: 0
    • Views: 207
    June 30th, 2016, 10:58 AM Go to last post
  25. DE1-SoC - HPS DMA example

    Started by nalkhateeb, June 16th, 2016 08:32 AM
    cyclone v, de1-soc, hps dma
    • Replies: 2
    • Views: 468
    June 24th, 2016, 12:00 PM Go to last post

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