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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 03:36 PM
    • Replies: 0
    • Views: 10,725
    October 14th, 2014, 03:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 02:37 PM
    • Replies: 0
    • Views: 30,072
    July 19th, 2013, 02:37 PM Go to last post
  1. Question Routing HPS I2C thru FPGA Not Working

    Started by mbp2014, September 14th, 2014 01:28 PM
    2 Pages
    1 2
    • Replies: 13
    • Views: 12,944
    May 19th, 2016, 04:04 AM Go to last post
  2. Cyclone V - EMAC ARP receive error

    Started by Altkl, May 14th, 2016 11:53 AM
    arp receive error, cyclone v, emac
    • Replies: 1
    • Views: 59
    May 16th, 2016, 05:43 AM Go to last post
  3. Read a wav file in an SD card with DE1 SoC

    Started by larryj, May 15th, 2016 05:14 PM
    • Replies: 0
    • Views: 62
    May 15th, 2016, 05:14 PM Go to last post
  4. Nios on DE0-Nano-SoC

    Started by naceradsky, May 14th, 2016 01:49 AM
    • Replies: 0
    • Views: 52
    May 14th, 2016, 01:49 AM Go to last post
  5. Cyclone V SoC - Shared Memory Controller

    Started by Taz1984, July 15th, 2013 10:20 PM
    5 Pages
    1 2 3 ... 5
    • Replies: 46
    • Views: 46,179
    May 11th, 2016, 05:43 PM Go to last post
  6. [SoCKit Cyclone V] HPS UART Controller to LTC connector

    Started by top94370, May 11th, 2016 04:54 AM
    • Replies: 0
    • Views: 26
    May 11th, 2016, 04:54 AM Go to last post
  7. Question Problem when programming Cyclone V (DE1-SoC)

    Started by franerto, February 24th, 2016 11:57 PM
    cyclone v, de1, programming, soc
    • Replies: 4
    • Views: 437
    May 11th, 2016, 03:40 AM Go to last post
  8. DE0 nano Cycl.V: SDRAM parameters for Qsys

    Started by tum_flo, May 11th, 2016 12:59 AM
    • Replies: 0
    • Views: 55
    May 11th, 2016, 12:59 AM Go to last post
  9. DE1-SoC HPS SDRAM memory mapping

    Started by Korn, March 19th, 2016 07:55 AM
    • Replies: 1
    • Views: 243
    May 10th, 2016, 07:17 PM Go to last post
    • Replies: 2
    • Views: 121
    May 9th, 2016, 06:23 AM Go to last post
    • Replies: 1
    • Views: 153
    May 6th, 2016, 05:45 AM Go to last post
    • Replies: 4
    • Views: 225
    May 3rd, 2016, 12:15 PM Go to last post
  10. Arrow SoCKit FPGA-to-HPS SDRAM (f2h_sdram) Help Needed!

    Started by christnp, August 25th, 2014 04:15 PM
    arrow, ddr3, f2h_sdram, fpga-to-hps, sdram
    • Replies: 6
    • Views: 14,340
    April 28th, 2016, 05:25 AM Go to last post
  11. Testing AXI custom component

    Started by flz47655, April 2nd, 2016 01:57 PM
    • Replies: 5
    • Views: 311
    April 28th, 2016, 05:15 AM Go to last post
  12. HPS pin current strength settings

    Started by ChrisKa, August 24th, 2015 11:40 PM
    • Replies: 1
    • Views: 583
    April 22nd, 2016, 07:55 AM Go to last post
  13. quartus_hps with qspi in quad mode

    Started by poster, April 18th, 2016 05:19 AM
    • Replies: 0
    • Views: 109
    April 18th, 2016, 05:19 AM Go to last post
  14. FPGA read data from HPS DDR3

    Started by Korn, April 13th, 2016 01:49 PM
    • Replies: 0
    • Views: 153
    April 13th, 2016, 01:49 PM Go to last post
  15. SOC evaluation board for learning

    Started by sherif123, April 12th, 2016 06:44 AM
    • Replies: 0
    • Views: 151
    April 12th, 2016, 06:44 AM Go to last post
  16. DE1-SoC HPS DDR3 Controller with UniPHY fitter error

    Started by Korn, April 10th, 2016 04:46 AM
    • Replies: 0
    • Views: 150
    April 10th, 2016, 04:46 AM Go to last post
  17. digital simulation model for Altera SoC (Arria 10)

    Started by amir_aa, March 24th, 2016 07:20 AM
    arm, arm core, arria 10, functional, verification
    • Replies: 2
    • Views: 260
    April 1st, 2016, 01:18 PM Go to last post
  18. Inject SDRAM ECC error on Cyclone V HPS

    Started by poster, March 30th, 2016 08:47 AM
    • Replies: 0
    • Views: 134
    March 30th, 2016, 08:47 AM Go to last post
  19. Accessing same memory address from HPS and FPGA

    Started by jocastro, February 25th, 2016 06:55 AM
    • Replies: 5
    • Views: 678
    March 18th, 2016, 01:59 AM Go to last post
  20. What is the TDP of a Cyclone V chip?

    Started by jocastro, March 17th, 2016 05:46 AM
    cyclone v
    • Replies: 0
    • Views: 211
    March 17th, 2016, 05:46 AM Go to last post
  21. Problems with NANO/ATLAS SOCKIT

    Started by abrueda, March 15th, 2016 06:51 AM
    • Replies: 0
    • Views: 190
    March 15th, 2016, 06:51 AM Go to last post
    • Replies: 0
    • Views: 199
    March 6th, 2016, 07:04 PM Go to last post
  22. swinfo2header defines no real addresses

    Started by jwiesemann, March 3rd, 2016 04:29 AM
    f2h, fpga2hps, h2f, hps2fpga, swinfo2header
    • Replies: 0
    • Views: 229
    March 3rd, 2016, 04:29 AM Go to last post
  23. HPS BareMetal EMAC driver

    Started by arkadish123, July 24th, 2014 01:27 PM
    emac
    • Replies: 3
    • Views: 14,270
    March 2nd, 2016, 11:58 PM Go to last post
  24. DE1-SOC Board for Beginners

    Started by rp.beltran, March 2nd, 2016 12:10 PM
    beginner, de1-soc, ram, soc
    • Replies: 0
    • Views: 246
    March 2nd, 2016, 12:10 PM Go to last post
  25. With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

    Started by aprado, June 17th, 2014 03:26 AM
    3 Pages
    1 2 3
    • Replies: 20
    • Views: 22,970
    February 19th, 2016, 08:36 AM Go to last post
  26. Arria10 HPS Fpga to Sdram cannot be configured above 64 bits

    Started by ganeshmirajkar, January 14th, 2016 05:20 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 1,098
    February 14th, 2016, 09:12 PM Go to last post

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