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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 03:36 PM
    • Replies: 0
    • Views: 12,198
    October 14th, 2014, 03:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 02:37 PM
    • Replies: 0
    • Views: 31,373
    July 19th, 2013, 02:37 PM Go to last post
    • Replies: 1
    • Views: 742
    January 11th, 2017, 11:35 AM Go to last post
  1. Question Routing of I2C0 pins on SoC

    Started by Luki B, December 22nd, 2016 12:10 AM
    i2c, qsys, routing, soc
    • Replies: 2
    • Views: 910
    January 10th, 2017, 05:43 AM Go to last post
  2. cpu0_deflags4 interrupt

    Started by wieant, January 4th, 2017 04:59 AM
    • Replies: 0
    • Views: 643
    January 4th, 2017, 04:59 AM Go to last post
  3. How to write data into DDR3 SDRAM-HPS!

    Started by NguyenNgocTan, April 18th, 2014 09:20 PM
    • Replies: 8
    • Views: 20,880
    January 4th, 2017, 12:38 AM Go to last post
  4. emac0 through FPGA

    Started by Thomas Reinemann, December 29th, 2016 07:21 AM
    emac fabric
    • Replies: 0
    • Views: 596
    December 29th, 2016, 07:21 AM Go to last post
  5. Linux -> mSGDMA -> Dual Clock FIFO

    Started by tomek160191, December 22nd, 2016 07:00 AM
    • Replies: 1
    • Views: 768
    December 27th, 2016, 09:55 AM Go to last post
  6. Connect TSE MAC to HPS

    Started by Tricky, November 28th, 2013 02:57 AM
    • Replies: 6
    • Views: 24,922
    December 12th, 2016, 04:03 AM Go to last post
  7. de2i-150-Custom IP accessing memory

    Started by albahr, December 6th, 2016 06:11 PM
    • Replies: 0
    • Views: 599
    December 6th, 2016, 06:11 PM Go to last post
  8. Question about Audio port

    Started by Taeyangchoi, November 30th, 2016 11:31 PM
    • Replies: 0
    • Views: 525
    November 30th, 2016, 11:31 PM Go to last post
  9. Altered Application Stored In SDRAM

    Started by reberp, November 23rd, 2016 07:04 AM
    • Replies: 0
    • Views: 460
    November 23rd, 2016, 07:04 AM Go to last post
  10. DE1-SoC HPS SDRAM memory mapping

    Started by Korn, March 19th, 2016 07:55 AM
    • Replies: 2
    • Views: 1,377
    November 15th, 2016, 05:53 AM Go to last post
    • Replies: 0
    • Views: 491
    November 14th, 2016, 05:51 AM Go to last post
  11. With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

    Started by aprado, June 17th, 2014 03:26 AM
    3 Pages
    1 2 3
    • Replies: 22
    • Views: 28,929
    November 7th, 2016, 09:01 AM Go to last post
  12. DE1-SoC IP problem

    Started by mohamedmsslk, November 5th, 2016 05:54 AM
    • Replies: 0
    • Views: 409
    November 5th, 2016, 05:54 AM Go to last post
  13. Testing AXI custom component

    Started by flz47655, April 2nd, 2016 01:57 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 2,306
    November 3rd, 2016, 05:01 AM Go to last post
  14. HPS CLK1 and CLK2 crystal oscillators

    Started by sherif123, October 29th, 2016 10:52 PM
    • Replies: 1
    • Views: 549
    October 31st, 2016, 10:44 PM Go to last post
    • Replies: 1
    • Views: 489
    October 18th, 2016, 11:38 AM Go to last post
  15. De0 Nano SoC

    Started by Umesh, October 8th, 2016 05:04 AM
    • Replies: 3
    • Views: 808
    October 12th, 2016, 04:43 PM Go to last post
  16. Route HPS UART pins to FPGA pins DE0 nano SoC

    Started by daniel45675, October 2nd, 2016 02:47 PM
    de0 nano soc, fpga, hps, route, uart
    • Replies: 5
    • Views: 1,296
    October 10th, 2016, 05:23 PM Go to last post
  17. use DS-5 AE Evaluation for C code programming on DE0-NANO_SOC

    Started by mojcmos, September 28th, 2016 04:00 AM
    • Replies: 0
    • Views: 636
    September 28th, 2016, 04:00 AM Go to last post
  18. How to enable SDRAM ECC in the Qsys

    Started by mojcmos, September 26th, 2016 03:34 AM
    • Replies: 4
    • Views: 668
    September 26th, 2016, 11:49 PM Go to last post
  19. Altera Cyclone V SoC FPGA Development Kit GPIO chip numbering

    Started by eldorr, September 26th, 2016 10:54 PM
    • Replies: 0
    • Views: 649
    September 26th, 2016, 10:54 PM Go to last post
  20. Terasic SATA/SAS HSMC Card Reference Project for Cyclone V SOC

    Started by redd, January 28th, 2016 12:42 PM
    cyclone v, hsmc, reference design, sata
    • Replies: 1
    • Views: 1,106
    September 23rd, 2016, 01:34 AM Go to last post
  21. Question How to generate boardinfo (xml) files?

    Started by Kunal Patwardhan, September 22nd, 2016 10:43 PM
    boardinfo, cyclone v soc, device tree source, dts
    • Replies: 1
    • Views: 635
    September 22nd, 2016, 11:41 PM Go to last post
    • Replies: 3
    • Views: 778
    September 21st, 2016, 05:33 PM Go to last post
  22. using h2f_axi_master

    Started by mojcmos, September 13th, 2016 10:11 PM
    • Replies: 0
    • Views: 475
    September 13th, 2016, 10:11 PM Go to last post
  23. How to Program Cyclone V SoC Dev Kit EPCQ256

    Started by kstolp, September 2nd, 2013 02:41 PM
    • Replies: 8
    • Views: 31,535
    September 12th, 2016, 05:12 AM Go to last post
  24. Cyclone V SoC Migration to Arria 10 SoC

    Started by johnie83, August 9th, 2016 07:10 AM
    arria 10, cyclone v
    • Replies: 1
    • Views: 800
    September 6th, 2016, 10:16 PM Go to last post
  25. need to License for ARM hard processor

    Started by mojcmos, August 28th, 2016 11:28 PM
    • Replies: 1
    • Views: 693
    September 6th, 2016, 10:09 PM Go to last post
  26. DE1-SoC HPS DDR3 Controller with UniPHY fitter error

    Started by Korn, April 10th, 2016 04:46 AM
    • Replies: 1
    • Views: 1,378
    September 6th, 2016, 07:29 PM Go to last post

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