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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 04:36 PM
    • Replies: 0
    • Views: 11,452
    October 14th, 2014, 04:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 03:37 PM
    • Replies: 0
    • Views: 30,675
    July 19th, 2013, 03:37 PM Go to last post
    • Replies: 0
    • Views: 34
    Today, 09:25 AM Go to last post
  1. Question How to configure the SPI on DE0-Nano-SoC

    Started by m3!_newbie, Yesterday 12:07 PM
    arm, de0-nano-soc, hps, spi, touchscreen
    • Replies: 0
    • Views: 33
    Yesterday, 12:07 PM Go to last post
  2. Cyclone V, HPS SPI routing to FPGA pins

    Started by Captain-Chaos, January 13th, 2017 02:35 AM
    • Replies: 0
    • Views: 60
    January 13th, 2017, 02:35 AM Go to last post
  3. Cyclone V SE Power management

    Started by nico94, January 13th, 2017 01:58 AM
    • Replies: 0
    • Views: 40
    January 13th, 2017, 01:58 AM Go to last post
  4. Cyclone V, DE1-SOC GPIO Header Pinout Diagram

    Started by sherrellbc, September 30th, 2014 09:40 PM
    • Replies: 4
    • Views: 13,523
    January 12th, 2017, 01:41 PM Go to last post
  5. Changing the HPS SDRAM PLL clock source from QSys

    Started by Daixiwen, January 11th, 2017 05:36 AM
    • Replies: 3
    • Views: 109
    January 12th, 2017, 01:33 AM Go to last post
  6. Help how to use avalon interface

    Started by gianluca87, January 10th, 2017 09:08 AM
    avalon, fpga, hps, soc
    • Replies: 3
    • Views: 129
    January 12th, 2017, 01:19 AM Go to last post
    • Replies: 1
    • Views: 101
    January 11th, 2017, 12:35 PM Go to last post
  7. CAN bus register DE0-Nano-SoC.

    Started by yassine_ensea, January 11th, 2017 02:07 AM
    • Replies: 0
    • Views: 58
    January 11th, 2017, 02:07 AM Go to last post
  8. Question Routing of I2C0 pins on SoC

    Started by Luki B, December 22nd, 2016 01:10 AM
    i2c, qsys, routing, soc
    • Replies: 2
    • Views: 146
    January 10th, 2017, 06:43 AM Go to last post
  9. cpu0_deflags4 interrupt

    Started by wieant, January 4th, 2017 05:59 AM
    • Replies: 0
    • Views: 68
    January 4th, 2017, 05:59 AM Go to last post
  10. How to write data into DDR3 SDRAM-HPS!

    Started by NguyenNgocTan, April 18th, 2014 10:20 PM
    • Replies: 8
    • Views: 19,739
    January 4th, 2017, 01:38 AM Go to last post
  11. emac0 through FPGA

    Started by Thomas Reinemann, December 29th, 2016 08:21 AM
    emac fabric
    • Replies: 0
    • Views: 112
    December 29th, 2016, 08:21 AM Go to last post
  12. Linux -> mSGDMA -> Dual Clock FIFO

    Started by tomek160191, December 22nd, 2016 08:00 AM
    • Replies: 1
    • Views: 136
    December 27th, 2016, 10:55 AM Go to last post
  13. Connect TSE MAC to HPS

    Started by Tricky, November 28th, 2013 03:57 AM
    • Replies: 6
    • Views: 23,983
    December 12th, 2016, 05:03 AM Go to last post
  14. de2i-150-Custom IP accessing memory

    Started by albahr, December 6th, 2016 07:11 PM
    • Replies: 0
    • Views: 133
    December 6th, 2016, 07:11 PM Go to last post
  15. Question about Audio port

    Started by Taeyangchoi, December 1st, 2016 12:31 AM
    • Replies: 0
    • Views: 136
    December 1st, 2016, 12:31 AM Go to last post
  16. Altered Application Stored In SDRAM

    Started by reberp, November 23rd, 2016 08:04 AM
    • Replies: 0
    • Views: 124
    November 23rd, 2016, 08:04 AM Go to last post
  17. DE1-SoC HPS SDRAM memory mapping

    Started by Korn, March 19th, 2016 08:55 AM
    • Replies: 2
    • Views: 906
    November 15th, 2016, 06:53 AM Go to last post
    • Replies: 0
    • Views: 165
    November 14th, 2016, 06:51 AM Go to last post
  18. With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

    Started by aprado, June 17th, 2014 04:26 AM
    3 Pages
    1 2 3
    • Replies: 22
    • Views: 26,525
    November 7th, 2016, 10:01 AM Go to last post
  19. DE1-SoC IP problem

    Started by mohamedmsslk, November 5th, 2016 06:54 AM
    • Replies: 0
    • Views: 144
    November 5th, 2016, 06:54 AM Go to last post
  20. Testing AXI custom component

    Started by flz47655, April 2nd, 2016 02:57 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 1,372
    November 3rd, 2016, 06:01 AM Go to last post
  21. HPS CLK1 and CLK2 crystal oscillators

    Started by sherif123, October 29th, 2016 11:52 PM
    • Replies: 1
    • Views: 225
    October 31st, 2016, 11:44 PM Go to last post
  22. Cyclone V SoC - Shared Memory Controller

    Started by Taz1984, July 15th, 2013 11:20 PM
    6 Pages
    1 2 3 ... 6
    • Replies: 50
    • Views: 51,666
    October 26th, 2016, 12:26 PM Go to last post
    • Replies: 1
    • Views: 210
    October 18th, 2016, 12:38 PM Go to last post
  23. De0 Nano SoC

    Started by Umesh, October 8th, 2016 06:04 AM
    • Replies: 3
    • Views: 413
    October 12th, 2016, 05:43 PM Go to last post
  24. High bandwidth data transfer between hps and fpga

    Started by mojcmos, September 8th, 2016 04:50 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 1,002
    October 12th, 2016, 08:28 AM Go to last post
  25. Route HPS UART pins to FPGA pins DE0 nano SoC

    Started by daniel45675, October 2nd, 2016 03:47 PM
    de0 nano soc, fpga, hps, route, uart
    • Replies: 5
    • Views: 498
    October 10th, 2016, 06:23 PM Go to last post
  26. use DS-5 AE Evaluation for C code programming on DE0-NANO_SOC

    Started by mojcmos, September 28th, 2016 05:00 AM
    • Replies: 0
    • Views: 287
    September 28th, 2016, 05:00 AM Go to last post

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