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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 04:36 PM
    • Replies: 0
    • Views: 13,325
    October 14th, 2014, 04:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 03:37 PM
    • Replies: 0
    • Views: 32,431
    July 19th, 2013, 03:37 PM Go to last post
  1. HPS SPI slave

    Started by simonkbrown, December 14th, 2017 09:26 AM
    device tree, driver, hps, interrupts, spi
    • Replies: 0
    • Views: 140
    December 14th, 2017, 09:26 AM Go to last post
  2. HPS vs FPGA configuration

    Started by rod@ariradesign.com, November 20th, 2017 01:45 PM
    • Replies: 3
    • Views: 336
    December 14th, 2017, 02:50 AM Go to last post
  3. storing the values in hps coming from fpga

    Started by dipin555, December 11th, 2017 10:10 PM
    • Replies: 0
    • Views: 127
    December 11th, 2017, 10:10 PM Go to last post
  4. Question Qsys HPS SDRAM and peripheral connections

    Started by agg, December 11th, 2017 02:26 PM
    • Replies: 0
    • Views: 122
    December 11th, 2017, 02:26 PM Go to last post
  5. SoC programming other devices

    Started by Pencol, December 11th, 2017 12:03 AM
    • Replies: 0
    • Views: 159
    December 11th, 2017, 12:03 AM Go to last post
  6. sending 64 bit from fpga to hs to terminal in pc @10k

    Started by dipin555, October 24th, 2017 04:51 AM
    • Replies: 3
    • Views: 561
    December 9th, 2017, 07:35 AM Go to last post
  7. HPS peripherals discription

    Started by lamazavr, December 7th, 2017 02:39 AM
    hps, peripherals description
    • Replies: 3
    • Views: 288
    December 8th, 2017, 06:30 PM Go to last post
  8. Sopc2dts "Transparent bridge not yet supported" meaning?

    Started by wobbert, December 1st, 2017 02:41 AM
    • Replies: 1
    • Views: 315
    December 6th, 2017, 02:58 AM Go to last post
  9. ARM Training

    Started by joe306, December 4th, 2017 10:12 AM
    • Replies: 0
    • Views: 156
    December 4th, 2017, 10:12 AM Go to last post
  10. Question Write/Read RAM memory from FPGA.

    Started by skliarovartem, November 11th, 2017 06:16 PM
    incip_memory2
    • Replies: 5
    • Views: 755
    November 26th, 2017, 12:14 PM Go to last post
  11. Question issues in running CycV_SoC with DDR3 RAM on Dev_Kit

    Started by MrFreshman, August 8th, 2014 04:17 AM
    cyclone v, ddr3, hcm, quartus
    • Replies: 3
    • Views: 17,570
    November 23rd, 2017, 08:02 AM Go to last post
  12. Question Can one board support an Arria 10 GX *or* an Arria 10 SX?

    Started by bgrattan, November 20th, 2017 04:00 PM
    arria 10, migration
    • Replies: 2
    • Views: 303
    November 21st, 2017, 10:19 AM Go to last post
  13. using the hps phy via loanios from fpga (de10-nano-soc)

    Started by letrend, November 21st, 2017 07:53 AM
    • Replies: 0
    • Views: 209
    November 21st, 2017, 07:53 AM Go to last post
  14. sopc2dts gives dts with 64bit address.

    Started by megahraj.ag, November 14th, 2017 12:45 AM
    arria10, device tree
    • Replies: 0
    • Views: 327
    November 14th, 2017, 12:45 AM Go to last post
    • Replies: 1
    • Views: 451
    November 10th, 2017, 04:04 AM Go to last post
  15. DE10 pins not found

    Started by D@n, November 3rd, 2017 02:52 PM
    • Replies: 6
    • Views: 683
    November 8th, 2017, 05:01 PM Go to last post
  16. Cyclone V SoC Preloader will not run bare metal app

    Started by jwdonal, September 5th, 2017 01:52 AM
    • Replies: 5
    • Views: 1,870
    November 8th, 2017, 01:53 PM Go to last post
  17. Can't load .jic file to EPCQ device.

    Started by krunal.gandhi, October 25th, 2017 03:15 AM
    • Replies: 2
    • Views: 643
    November 5th, 2017, 08:32 PM Go to last post
  18. sdram addressing troubles

    Started by adrenalin, November 1st, 2017 01:53 AM
    • Replies: 0
    • Views: 404
    November 1st, 2017, 01:53 AM Go to last post
  19. How to set up shared on-chip memory

    Started by sonicsmooth, August 3rd, 2017 10:33 AM
    • Replies: 2
    • Views: 1,006
    October 27th, 2017, 08:18 AM Go to last post
  20. Can HPS verify FPGA configuration?

    Started by mglapa, October 26th, 2017 05:18 PM
    • Replies: 1
    • Views: 395
    October 27th, 2017, 01:40 AM Go to last post
  21. Loading rbf file on boot from within Linux...

    Started by EauContraire, October 17th, 2017 04:28 AM
    • Replies: 0
    • Views: 480
    October 17th, 2017, 04:28 AM Go to last post
    • Replies: 3
    • Views: 907
    October 16th, 2017, 05:06 AM Go to last post
  22. Cyclone V SoC HPS2FPGA AXI Master - How to enable?

    Started by kstolp, September 12th, 2013 09:41 AM
    • Replies: 5
    • Views: 33,641
    October 15th, 2017, 08:43 PM Go to last post
  23. Cyclone V SoC DK: how to configure awprot/arprot of EMAC?

    Started by Aquu9, October 13th, 2017 08:30 AM
    • Replies: 0
    • Views: 329
    October 13th, 2017, 08:30 AM Go to last post
  24. How to let FPGA get access to HPS pins

    Started by davidc85, March 27th, 2014 05:44 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 32,415
    September 29th, 2017, 10:16 AM Go to last post
  25. sdram DE0-nano - PLL phase shift

    Started by JeanValjean, September 27th, 2017 01:08 PM
    • Replies: 0
    • Views: 486
    September 27th, 2017, 01:08 PM Go to last post
  26. Does User clock frequency in QSYS for HPS-to-FPGA clock work?

    Started by mawillia, February 26th, 2014 05:31 AM
    • Replies: 2
    • Views: 19,456
    September 25th, 2017, 12:45 AM Go to last post
  27. HPS - FPGA used inside block diagram file.

    Started by ruben.vinuela, March 18th, 2015 10:52 AM
    • Replies: 3
    • Views: 3,732
    September 2nd, 2017, 08:52 AM Go to last post
  28. DE1-SOC power button non-functioning in AS/EPCS mode

    Started by Micks, August 31st, 2017 06:24 AM
    active serial, de1-soc, epcs, power button
    • Replies: 0
    • Views: 651
    August 31st, 2017, 06:24 AM Go to last post

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