I'm working on a design with 64 LVDS signals. The Cyclone III I'm working on is a EP3C120F768. Two signals belong to each others (one is a clock output signal and the other is a data in signal). Because we want to use parallel flash for configuration quite a few pins are already used. Banks 2, 3, 4 and 5 are free to use for the LVDS signals.
I wanted to place an output signal directly beside a corresponding input signal but the synthesis tool complained about invalid placement of output pins. Currently I have all output pins on bank 2 and 5 (left and right banks) and the input pins are all located at banks 3 and 4. But I think this placement would be a nightmare for the layouter.
Can anyone give me some hints on what options I have to place pins?
If needed I can upload my current placement file.