We have a cyclone III device and a CPLD which controls the reset pins of the vhdl blocks and the NIOS II CPU in that device after power on. The program in CPLD looks CONF_DONE pin to understand FPGA configuration is completed or not.
Now, we want to use remote system upgrade and want to understand the reconfiguration finishes or not by looking at CONF_DONE pin or others pin. We have tested CONF_DONE pin in reconfiguration. It goes low to high when factory image is configured on FPGA after power on, but it never goes low after we reconfigure FPGA with the application image.
The question is how can we understand the application image is configured to FPGA after reconfiguration?