I have created the following shift register using Quartus II 8.0:
ENTITY ShiftReg IS
DATA_SIZE : INTEGER := 8
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
data_in : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (DATA_SIZE - 1 DOWNTO 0)
ARCHITECTURE ShiftReg OF ShiftReg IS
SIGNAL data_wire : STD_LOGIC_VECTOR (DATA_SIZE - 1 DOWNTO 0);
PROCESS (clk, clr, data_in, data_wire)
VARIABLE count_data : INTEGER;
IF (clr = '1') THEN
data_wire <= (OTHERS =>'0');
IF (clk'EVENT AND clk = '1') THEN
data_wire(DATA_SIZE - 1 DOWNTO 1) <= data_wire(DATA_SIZE - 2 DOWNTO 0);
data_wire(0) <= data_in;
data_out <= data_wire;
Performed the simulation using Altera-ModelSIM 6.6c and obtained the "correct" results as shown in Fig. 1.
After creating a new project and compile it using Quartus II 10.1, I have performed a new simulation (same stimuli) and obtained the "incorrect" behaviour as shown in Fig. 2.
Used Timequest to guide the placement and verified with the Technology Map Viewer (post-fiiting) that the resource usage and netlist are indeed the same in both version of Quartus (clearly the device used was also consistent EP1C12Q240C7).
Is this a problem related with the simuation tool and its libraries? what is that I am missing?
Thanks in advance for any reply