Dac help needed to generate sine waveform from Altera FPGA

[rbanerjee2]

Hi,
My application needs to generate a sine wave of 10 to 20 samples per period. I am using Altera Cyclone 3 FPGA. Can anyone suggest which DAC I should be using. Also inputs as to how to go about the process will be useful. I know that a look-up table would have to be built which contains these values. However a detailed process would be very highly appreciated. Also if the most popular DACs that are used with these applications are mentioned, then it will lessen a lot of burden on me.

Regards
Ranjan

[dwh@ovro.caltech.edu]

You need to do a little more research on your own first. You have missed several critical requirements, i.e., what is your highest frequency output (that you happen to want 10 or 20 samples at) and what is the dynamic range you require (this determines the number of bits in the DAC).

You could also work backwards; look at the ADC/DAC boards that Terasic has, and see if they are sufficient.

Cheers,
Dave

[rbanerjee2]

Hello,
I did a bit of research and I have decided for the initial part to use a lookup table and input the values to the DAC. I dont intend to implement a DDS at the very beginning. The frequency of the sine wave is going to be around 60Mhz and I will be using a 14bit DAC from Terasic (The one which is compatible to Altera Cyclone 3 FPGA starter kit with HSMC connector). I need to know how many samples will be ideal per cycle for a fairly clean sinwave to be seen at the scope . Also to represent the negative part of the sine wave, I must use 2's complement representation. Will the DAC take that into account? I mean if I represent a number in 2's complement form will the DAC understand that or take that as a positive number? Also say I have the magnitude of sine wave at a particular time to be 0.4583. If I multiply it by 1000 and store 4583 as shown in many posts, how will the DAC know that it has to represent 0.4583 and not 4583, or is it the relative values that are taken into account by the DAC? If someone can address these doubts, I would be very thankful.

Regards,
Ranjan

[dwh@ovro.caltech.edu]

The frequency of the sine wave is going to be around 60Mhz and I will be using a 14bit DAC from Terasic (The one which is compatible to Altera Cyclone 3 FPGA starter kit with HSMC connector).

And this DAC has a sample rate of what?

I need to know how many samples will be ideal per cycle for a fairly clean sinewave to be seen at the scope.

If your scope has a high bandwidth, then you will never see a 'clean' sinewave, you will see a staircase waveform that follows the sample values that you output. That is all a DAC can do. It is up to you to follow the DAC output with an analog filter to remove the frequencies that you do not want.

For example, read page 16:

http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf

Also to represent the negative part of the sine wave, I must use 2's complement representation. Will the DAC take that into account?

Read the DAC data sheet. There are several different binary formats. If the DAC does not accept 2's compliment, then worst case you'll just have to add an offset or flip the MSB.

Cheers,
Dave

[rbanerjee2]

Thanks a lot Dave for your useful insight. Right now the terasic site is down and I cannot access the datasheet. I will do so as soon as the site revives and let you know the details.
Regards,
Ranjan