I have to load my design into a cart that contains 2 FPGA stratix IV so i will use the Analysis and Synthesis tool and generate the verilog quartus mapping file (VQM) that will be divided with a partitioning tool into two parts to be probably the inputs of the fitter tool of the two FPGA's.
For more clarifications let's see the flow in the attachement.
So my question is :Could I use the vqm file as an input of the fitter tool? if it is possible could you tell me how can i do it?
I use the GUI and the Tcl commands to configurate my design.
Thank you for your help and if you need any information don't hesitate to ask me.