How to instantiate my SOPC hardware

[pob_klk]

Hi,

i'm all new at FPGAs, it's only been a few days since i'm working on it so i started reading some tutorials.

I successfully managed to light on a led by using a switch thanks to the tutorial named "Introduction to the Altera SOPC Builder Using Verilog Design". So i wanted to start something a little bit more complicated.

I created a new Quartus II project named "project7". Then, i used SOPC Builder to create my hardware, however i really don't know how to instantiate it using verilog.

I tried to adapt the file "nios_system_inst.v" from my previous project which was :

// Implements a simple Nios II system for the DE2 board.
// Inputs: SW7−0 are parallel port inputs to the Nios II system
// CLOCK_50 is the system clock
// KEY0 is the active-low system reset
// Outputs: LEDG7−0 are parallel port outputs from the Nios II system

module lights (SW, KEY, CLOCK_50, LEDG);

input [7:0] SW;
input [0:0] KEY;
input CLOCK_50;
output [7:0] LEDG;

// Instantiate the Nios II system module generated by the SOPC Builder:
// nios_system (clk, reset_n, out_port_from_the_LEDs, in_port_to_the_Switches)

nios_system NiosII (CLOCK_50, KEY[0], LEDG, SW);

endmodule

The file that i wrote is the following :

module nios_system0 (
                     // 1) global signals:
                      CLOCK_50,
                      KEY,

                     // the_hex0
                      HEX0,

                     // the_hex1
                      HEX1,

                     // the_hex2
                      HEX2,

                     // the_hex3
                      HEX3,

                     // the_lcd
                      LCD_EN,
                      LCD_RS,
                      LCD_RW,
                      LCD_DATA,

                     // the_leds
                      LEDG,

                     // the_switches
                      SW
                   )
;
input CLOCK_50;
input [0:0] KEY;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output LCD_EN;
output LCD_RS;
output LCD_RW;
inout [7:0] LCD_DATA;
output [7:0] LEDG;
input [7:0] SW;


nios_system NiosII (CLOCK_50, KEY[0], 
					HEX0, HEX1, HEX2, HEX3, 
					LCD_EN, LCD_RS, LCD_RW, LCD_DATA, 
					LEDG, SW);

endmodule

However it does not work. Indeed, when i check the pin assignments, i realize that almost none of the pins has been "connected" (because there is a question mark in front of the pin names).

I know that i'm not really clear about what i'm saying but i'm all new at FPGAs so it is still a little bit complicated for me

Some information :
I am using a DE2 board with Quartus II 9.0 (web edition)

Thank you in advance

[dwh@ovro.caltech.edu]

Try this tutorial:

http://www.alterawiki.com/wiki/Using...aster_Tutorial

There's a DE2 example in there.

Cheers,
Dave