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Thread: Newbie Verilog Q regarding Memory Accesses

  1. #1
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    Default Newbie Verilog Q regarding Memory Accesses

    Have developed a module with a memory element as follows:
    reg page_0_statement [65535:0];

    I am attempting to access the memory from a NIOS C application as a 32 bit unsigned int. Therefore, when an address comes from the CPU, I would like to read 32 bits by using the 11 LSBs of the address as an 32 bit multiplier into the memory. For example, if the cpu address is 0, I would want to read bits 0 - 31 of the memory. If the cpu address is 1, I would like to read bits 32 - 63, etc.

    My implementation looks like:

    cpu_bank_address <= {sc_address[10:0],{5{1'b0}}};
    if (~wr) // Active low WE
    page_0_statement[cpu_bank_address] <= sc_writedata;
    else
    sc_readdata <= page_0_statement[cpu_bank_address];

    sc_writedata and sc_readdata are part of an avalon MM slave. In addition, I omitted the chip select qualifier from this post (it's in the code).

    In the SW, I am simply trying to write an incrementing pattern to the entire RAM bank (Address 0 = 0; Address 1 = 1, Address 2 = 2, etc. However, what I get is Address 0 = 0; Address 1 = 2, Address 2 = 0; Address 3 = 2, etc.: The 0,1 pattern repeats over and over).

    I hard coded a read of 0xdeadbeef from a series of the locations. This appears to work. Therefore, I am fairly confident the the MM slave is functioning correctly (I have other, simpler compnenets that access MM slaves that work).

    A couple of Q's:
    Is the "calculation" of cpu_bank_address valid based on my design (Am happy to add details if required). In other words, should an address from the MM slave of 0 write/read the first 32 bits of the memeory array, an address of 1 the second 32 bits, etc.? If not, any guidance would be appreciated.

    Is it valid to use this as an offset into the memory array? If not, any guidance would be appreciated.

    As I am a Verilog Newbie, is there a better approach? If so, please be descriptive. It would be very helpful as primer research.

    Many thanks in advance,
    ME

  2. #2
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    Default Re: Newbie Verilog Q regarding Memory Accesses

    BTW, cpu_bank_address is defined as reg [15:0]

  3. #3
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    Default Re: Newbie Verilog Q regarding Memory Accesses

    I'm not familiar with Verilog, but how did you define page_0_statement?
    You should be able to define it as an array of 32-bit vectors and then directly use the address from the Avalon MM slave as index without adding padding 0s.
    It can be a good idea to use Signaltap probes on your component to see what's happening when your software accesses the component.

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