The execution time of software

[robocon]

I am using DE2 device. I have built a SOPC system. Through nios II, I'm trying to create a simple process and send this process to FPGA board.

       IOWR(PI_Control_BASE,0,0); // Send zero to GPIO of FPGA
       PI_val=PI_control(500); // PI_control is a subsystem
       IOWR(PI_Control_BASE,0,1); // Send one to GPIO of FPGA

The purpose of this action is I want to measure the execution time of PI_control when we use software implement.
When I change the interrupt time of Nios, the execution time of PI_control also change.
Can you have any idea to check the execution time of software?

[dsl]

The execution times are reasonably fixed (and determinable) provided that:
1) there is no contention for Avalon slaves
2) there are no delays waiting for anything external (eg JTAD UART)
3) the cache transfers are the same
4) the branch predictor behaves the same way.

To get trully determinable execution times you need to use tightly coupled memory for code and (most) data, and to disable the dynamic branch prediction.

[robocon]

Thank you very much.
In my system, I have only one output was connected to GPIO for get the signal (the execution time - signal = 1 the function are processing, signal =0 the function aren't processing). From that information I found the execution time of my process.
the procedure of my system below:
Firstly, Nios II sends zero to FPGA ~~~~> Secondly, Nios II processes the function (which I need to know the execution time) ~~~~> Thirdly, Nios II sends one to FPGA.
The signal (0 and 1) was sent from Nios to FPGA, I can measure from the GPIO of FPGA board.

The execution times are reasonably fixed (and determinable) provided that:
1) there is no contention for Avalon slaves

Can you tell me more information about this?

2) there are no delays waiting for anything external (eg JTAD UART)

In FPGA board I have only one SOPC and one pin connect to 1 GPIO

3) the cache transfers are the same

What is the cache transfers. Where can I check it?

4) the branch predictor behaves the same way.

What is the branch predictor behaves?

To get trully determinable execution times you need to use tightly coupled memory for code and (most) data, and to disable the dynamic branch prediction.

I didn't have any code In FPGA board accept SOPC and one output.