[pete123]

Hi,
I'm currently trying my luck with writing an avalon slave - however I'm not 100% sure wether my slave works correctly or not.

So I was wondering wether there is some kind of testbench(generator) available with which I can simulate and test my design - in regard to the communication with the avalon bus.

I know I could write a testbench, which stimulates my design as described in the specification, however I'd rather rely on an existing one.
(It's hard to proof something to be correct, when you can't proof the correctness of your proof

Thanks,
Petey

[Hardik]

Hi,

Please take a review of Avalon verification IP suit from below link.
http://www.altera.com/literature/lit-ug.jsp

This verification suit very your avalon slave / master interface.

Regards,
Hardik

[pete123]

Hi,

thanks for your hint! I already had a look at it and it seems that it is exactly the thing I was looking for.

However I can't get the tutorial to work :/
When I run the script.do in ModelSim (PE Student Edition 6.5a) I get these messages:

# Top level modules:                                                
#       master_bfm_tb                                               
# vsim work.master_bfm_tb                                           
# Loading sv_std.std                                                
# Loading work.verbosity_pkg                                        
# Loading work.avalon_mm_pkg                                        
# Loading work.master_bfm_tb                                        
# Loading work.test_bench                                           
# Loading work.master_bfm_sopc                                      
# Loading work.master_bfm_m0_arbitrator                             
# Loading work.master_bfm                                           
# Loading work.altera_avalon_mm_master_bfm                          
# Loading work.master_bfm_sopc_burst_0_upstream_arbitrator          
# Loading work.burstcount_fifo_for_master_bfm_sopc_burst_0_upstream_module
# Loading work.rdv_fifo_for_master_bfm_m0_to_master_bfm_sopc_burst_0_upstream_module
# Loading work.master_bfm_sopc_burst_0_downstream_arbitrator                        
# Loading work.master_bfm_sopc_burst_0                                              
# Loading work.ram_s1_arbitrator                                                    
# Loading work.ram                                                                  
# Loading work.altsyncram                                                           
# Loading work.ALTERA_DEVICE_FAMILIES                                               
# Loading work.ALTERA_MF_MEMORY_INITIALIZATION                                      
# Loading work.master_bfm_sopc_reset_clk_0_domain_synch_module                      
# ** Warning: (vsim-3017) ram.v(62): [TFMPC] - Too few port connections. Expected 23, found 7.
#         Region: /master_bfm_tb/tb/DUT/the_ram/the_altsyncram                                
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'wren_b'.          
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'rden_a'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'rden_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'data_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'address_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'clocken1'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'clocken2'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'clocken3'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'aclr0'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'byteena_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'addressstall_a'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'addressstall_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'q_b'.
# ** Warning: (vsim-3722) ram.v(62): [TFMPC] - Missing connection for port 'eccstatus'.
# .main_pane.wave.interior.cs.body.pw.wf
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: - Hello from altera_avalon_mm_master_bfm
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   $Revision: #2 $
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   $Date: 2009/08/28 $
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   AV_ADDRESS_W             = 16
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   AV_SYMBOL_W              = 8
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   AV_NUMSYMBOLS            = 4
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   AV_BURSTCOUNT_W          = 3
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_READ                 = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_WRITE                = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_ADDRESS              = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_BYTE_ENABLE          = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_BURSTCOUNT           = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_READ_DATA            = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_READ_DATA_VALID      = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_WRITE_DATA           = 1
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_BEGIN_TRANSFER       = 0
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_BEGIN_BURST_TRANSFER = 0
#                    0: INFO: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.hello: -   USE_WAIT_REQUEST         = 1
#                    0: INFO: ------------------------------------------------------------
# ** Warning: (vsim-3534) [FOFIR] - Failed to open file "../ram.hex" for reading.
# No such file or directory. (errno = ENOENT)    : c:/altera/91/quartus/eda/sim_lib/altera_mf.v(792)
#    Time: 0 ps  Iteration: 0  Instance: /master_bfm_tb/tb/DUT/the_ram/the_altsyncram
# ERROR: cannot read ../ram.hex.
# ** Warning: (vsim-7) Failed to open readmem file "../ram.ver" in read mode.
# No such file or directory. (errno = ENOENT)    : c:/altera/91/quartus/eda/sim_lib/altera_mf.v(43706)
#    Time: 0 ps  Iteration: 0  Instance: /master_bfm_tb/tb/DUT/the_ram/the_altsyncram
#                    0:  verbosity_pkg.set_verbosity: Setting Verbosity level=4 (VERBOSITY_INFO)
#               250000: FAILURE: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.drive_request: Burst Count must be set > 0
#               250000: FAILURE: master_bfm_tb.tb.DUT.the_master_bfm.master_bfm.drive_request: Burst Size must be set > 0
#               250000: FAILURE: avalon_mm_pkg.abort_simulation: Abort the simulation due to fatal error incident.
# Break in Function abort_simulation at C:/altera/91/ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv line 69
# Simulation Breakpoint: Break in Function abort_simulation at C:/altera/91/ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv line 69
# MACRO ./script.do PAUSED at line 8

I could remove the file not found by simply editing the ram.v, but the other error messages remain unsolved.
Any ideas? Can someone maybe walk-me-through via skype/icq?

Thanks,
Pete

[htian]

"
# No such file or directory. (errno = ENOENT) : c:/altera/91/quartus/eda/sim_lib/altera_mf.v(792)
"

Make sure the directory
c:/altera/91/quartus/eda/sim_lib
is correct in your PC first.

[pete123]

Hi,

okay I got the example to work - using it under linux

However my next problem is that my design is VHDL-based whereas the Avalon MM Master BFM is generated as Verilog (even if I request VHDL) and the ModelSim by Altera provides only support for one HDL --> I can't mix VHDL and Verilog.

Any ideas how I can test my design?

Current status is when I read from my slave it returns the data I've written to it just a few moments ago - although readdata is tied to a constant value ? Any Ideas?

Thanks,
Pete
(p.s.: sorry for the long delay)