[cLaRe]

Hi,

Recently Im trying to use TimeQuest Timing Analyzer in order to the Fmax achievable by my design. Im using Quartus 7.2 sp 3. I have tried out the common tutorial file available from Altera website. But I dunno why I cant have the result I want. It appears that I have "No paths to report" in the reports.

From those tutorial sheet, it only mention how to Insert Constraint for Create Clock. Apart from that, I have nothing else for my SDC files. I believe that's the reason for having "No paths to report".

Its there any simple and straight forward help in writing SDC file? I only wanted to check the Fmax achievable by my design

Thank you very much

[amilcar]

Yes, there is one on-line, free course that explains what you want: http://www.altera.com/customertraini...st/player.html

[cLaRe]

Thanks alot.

I have roughly gone through the video. I guess the biggest challenge is how to get get the SDC file done. Of which I still done quite get it.

[amilcar]

If your design has a single clock, all you need to do is to constrain it and the tool will automatically tell you if your design meets the timing that you used for the clock.
The you can use the slack information to calculate the Fmax.

But you really need to see all the video, carefully, and not roughly.

[cLaRe]

Thanks. I have got it done! Just one final question:

when i constraint the out IO path as:

set_output_delay -clock {clock} 0 [all_outputs]

meaning i would like to have the delay value 0ns

this is practically possible?

[kaz]

Yes, it is possible if you are lucky with the fitter. Particularly easy with DDR interface when data and clock are generated with same delay.

The question is why should the output data and clock be dead edge aligned?

You better set delay according to destination register of external device.

ignoring board differences of data/clk delay then you should set
maximum delay = Tsu of external register and
minimum delay = hold time of external register.

The fitter hopefully will then insert the required delay.

[cLaRe]

Originally Posted by kaz

Yes, it is possible if you are lucky with the fitter. Particularly easy with DDR interface when data and clock are generated with same delay.

The question is why should the output data and clock be dead edge aligned?

You better set delay according to destination register of external device.

ignoring board differences of data/clk delay then you should set
maximum delay = Tsu of external register and
minimum delay = hold time of external register.

The fitter hopefully will then insert the required delay.

do I get to know the Tsu and Thd of the external register? it is a fixed value?

[kaz]

Every external device has its own spec.
some give setup/hold figures(at their pins, and this what matters). Others tell you the actual data delay required e.g edge aligned or how far behind clock is tolerated.
You may also have another fpga as external device in which case the setup/hold are configurable (through delay inserted by fpga) and then you can try the fitter with your chosen values.

some other devices(ADCs for example) have timing tracking circuitry that can adjust timing automatically. they either rotate the incoming clock or delay data like fpgas

[cLaRe]

Originally Posted by kaz

Every external device has its own spec.
some give setup/hold figures(at their pins, and this what matters). Others tell you the actual data delay required e.g edge aligned or how far behind clock is tolerated.
You may also have another fpga as external device in which case the setup/hold are configurable (through delay inserted by fpga) and then you can try the fitter with your chosen values.

some other devices(ADCs for example) have timing tracking circuitry that can adjust timing automatically. they either rotate the incoming clock or delay data like fpgas

thank you very much! at least now i got the rough idea. i'll do more study on this again =)

[cLaRe]

one last question, t_hold and t_setup are required for pin-register and register-register. what about pin-pin?