[vgs]

Hi,

Assuming timing closure is the issue, there is also an .sdc file for the Frame Buffer which might help in your case. You should clean timing errors before you try debugging the issue further.

If you are not using triple buffers (with drop and repeat on) then the input frame rate and the output frame rate must be the same and the PLL that creates the output clock should be driven by your input clock (otherwise you will get glitches when the input and output clocks drift apart from each other).

I believe you have more than enough memory bandwidth but did you do the computation? Is your design working with only one input on? jakobjones posted an excel sheet to do the bandwidth calculation a while ago. You could also try to increase the FIFO depth and burst target parameters of the frame buffers but this is a long shot. Make sure that you did not set the FIFO depth to be equal to the burst target.

Kind regards